MediaBreeze: a decoupled architecture for accelerating multimedia applications

ABSTRACT

Decoupled architectures are fine-grain processors that partition the memory access and execute functions in a computer program and exploit the parallelism between the two functions. Although some concepts from the traditional decoupled access execute paradigm made its way into commercial processors, they encountered resistance in general-purpose applications because these applications are not very structured and regular. However, multimedia applications have recently become dominant workload on desktops and workstations. Media applications are very structured and regular and lend themselves well to the decoupling concept. In this paper, we present an architecture that decouples the useful/true computations from the overhead/supporting instructions in media applications. The proposed scheme is incorporated into an out-of-order general-purpose processor enhanced with SIMD extensions. Explicit hardware support is provided to exploit instruction level parallelism in the overhead component. Performance evaluation shows that such hardware can significantly improve performance over conventional SIMD enhanced general-purpose processors. Results on nine multimedia benchmarks show that the proposed MediaBreeze architecture provides a 1.05x to 16.7x performance improvement over a 2-way out-of-order SIMD machine. On introducing slip-based data prefetching, a performance improvement up to 28x is observed.

REFERENCES

• 1: James E. Smith, Decoupled access/execute computer architectures, ACM Transactions on Computer Systems (TOCS), v.2 n.4, p.289-308, Nov. 1984 [doi>10.1145/357401.357403]
• 2: James E. Smith , Shlomo Weiss , Nicholas Y. Pang, A simulation study of decoupled architecture computers, IEEE Transactions on Computers, v.35 n.8, p.692-702, Aug. 1986 [doi>10.1109/TC.1986.1676820]
• 3: Lizyamma Kurian, Issues in the design of a decoupled architecture for a Risc environment, Pennsylvania State University, University Park, PA, 1993
• 4: Harvey G. Cragon , W. Joe Watson, The TI Advanced Scientific Computer, Computer, v.22 n.1, p.55-64, January 1989 [doi>10.1109/2.19823]
• 5: A. R. Pleszkun and E. S. Davidson, "Structured memory access architecture," Proc. IEEE. Int. Conf. on Parallel Processing, pp. 461-471, 1983.
• 6: R. R. Shively, "Architecture of a programmable digital signal processor," IEEE Trans. on Computers, vol. C-31, pp. 16-22, Jan. 1978.
• 7: J. R. Goodman , Jian-tu Hsieh , Koujuch Liou , Andrew R. Pleszkun , P. B. Schechter , Honesty C. Young, PIPE: a VLSI decoupled architecture, Proceedings of the 12th annual international symposium on Computer architecture, p.20-27, June 17-19, 1985, Boston, Massachusetts, United States
• 8: J. E. Thornton, "Parallel operation in the Control Data 6600," Fall Joint Computers Conference, vol. 26, pp. 33-40, 1961.
• 9: Yinong Zhang , George B. Adams, III, Performance modeling and code partitioning for the DS architecture, Proceedings of the 25th annual international symposium on Computer architecture, p.293-304, June 27-July 02, 1998, Barcelona, Spain
• 10: Wm. A. Wulf, Evaluation of the WM architecture, Proceedings of the 19th annual international symposium on Computer architecture, p.382-390, May 19-21, 1992, Queensland, Australia
• 11: D. J. Kuck, and R. A. Stokes, "The Burroughs scientific processor (BSP)," IEEE Trans. on Computers, C-31 (5), pp. 363-376, 1982.
• 12: Parthasarathy Ranganathan , Sarita Adve , Norman P. Jouppi, Performance of image and video processing with general-purpose processors and media ISA extensions, Proceedings of the 26th annual international symposium on Computer architecture, p.124-135, May 01-04, 1999, Atlanta, Georgia, United States
• 13: D. Burger, and T. M. Austin, "The SimpleScalar tool set," Version 2.0. Technical Report 1342, Univ. of Wisconsin-Madison, Comp. Sci. Dept, 1997.
• 14: D. Talla, "Architectural techniques to accelerate multimedia applications on general-purpose processors," Ph.D. Thesis, The University of Texas at Austin, Aug. 2001. Available: http://www.ece.utexas.edu/-deepu/phd_thesis.pdf
• 15: Phil Lapsley , Jeff Bier , Amit Shinham , Edward A. Lee , Amit Shoham , Amit Shohsm, DSP Processor Fundamentals: Architectures and Features, Wiley-IEEE Press, 1996
• 16: Sally Anne McKee, Maximizing memory bandwidth for streamed computations, University of Virginia, Charlottesville, VA, 1996
• 17: Jesus Corbal , Roger Espasa , Mateo Valero, On the Efficiency of Reductions in µ-SIMD Media Extensions, Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques, p.83, September 08-12, 2001
• 18: R. B. Lee, "Multimedia extensions for general-purpose processors," Proc. IEEE Workshop on Signal Processing Systems, pp, 9-23, Nov. 1997.
• 19: Cost-Effective Hardware Acceleration of Multimedia Applications, Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors, p.415, September 23-26, 2001

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Single-instruction-stream, multiple-data-stream processors (SIMD)

Additional Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Performance attributes

General Terms:
Design, Performance

Keywords:
SIMD, access and execute mechanisms, decoupling, general-purpose processors, hardware accelerators, microprocessor design, multimedia, prefetching