Hierarchical registers for scientific computers

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Hierarchical registers for scientific computers

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International Conference on Supercomputing archive
Proceedings of the 2nd international conference on Supercomputing table of contents

St. Malo, France

Pages: 346 - 354

Year of Publication: 1988

ISBN:0-89791-272-1

Authors

J. A. Swensen	Univ. of California, Berkeley, CA
Y. N. Patt	Univ. of California, Berkeley, CA

Sponsor

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 20, Citation Count: 14

Additional Information:

abstract references cited by index terms collaborative colleagues

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ABSTRACT

Simulations of scientific programs running on traditional scientific computer architectures show that execution with hundreds of registers can be more than twice as fast as execution with only eight registers. In addition, execution with a small number of fast registers and hundreds of slower registers can be as fast as execution with hundreds of fast registers. A hierarchical organization of fast and slow registers is presented, register-allocation strategies are discussed, and a novel, indirect, register-addressing mechanism is described.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Control Data Corporation, Control Data 7600 Computer System: Preliminary Reference Manual, Control Data Corporation, Minneapolis (circa 1970).
	2	Cray Research, inc., "Cray-1 Computer Systems: Cray-1 S Series Hardware Reference Manual," HR- 0808, Mendota Heights, Minn. (1981).
	3	Cray Research, Inc., "Cray Computer Systems: Cray X-MP Model 48 Mainframe Reference Manual,'~ HR-0097, Mendota Heights, Minn. {1984).
	4	Cray Research, Inc., "Cray Computer Systems: Cray-2 Hardware Reference Manual," HR-2000, Mendota Heights, Minn. (198,5).
	5	Denelcor, Inc., "HEP Hardware Reference Manual," 9000003, Denver (1982).
	6	ETA Systems, Inc., "Mainframe Subsystem Equipment Specification," 003106, St. Paul, Minn. {February 27, lg87).
	7	ETA Systems, Inc., "Mainfrar~ne Subsystem Instruction Specification for the ETA'"," 000211, St. Paul, Minn. (June 4, 1987).
	8	David L. Kuck, Structure of Computers and Computations, John Wiley & Sons, Inc., New York, NY, 1978
	9	F.H. MeMahon, "LLNL FORTRANS KERNELS' MFLOPS," Lawrence Livermore National Laboratory {March 1984).
	10	John Alan Swensen, High-bandwidth/low-latency temporary storage for supercomputers, 1987

CITED BY 14

	A. R. Pleszkun , G. S. Sohi, Multiple instruction issue and single-chip processors, Proceedings of the 21st annual workshop on Microprogramming and microarchitecture, p.64-66, November 28-December 02, 1988, San Diego, California, United States
	Javier Zalamea , Josep Llosa , Eduard Ayguadé , Mateo Valero, Two-level hierarchical register file organization for VLIW processors, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.137-146, December 2000, Monterey, California, United States
	Matthew Postiff , David Greene , Steven Raasch , Trevor Mudge, Integrating superscalar processor components to implement register caching, Proceedings of the 15th international conference on Supercomputing, p.348-357, June 2001, Sorrento, Italy
	José-Lorenzo Cruz , Antonio González , Mateo Valero , Nigel P. Topham, Multiple-banked register file architectures, ACM SIGARCH Computer Architecture News, v.28 n.2, p.316-325, May 2000
	Josep Llosa , Mateo Valero , Eduard Ayguadé , Antonio González, Hypernode reduction modulo scheduling, Proceedings of the 28th annual international symposium on Microarchitecture, p.350-360, November 29-December 01, 1995, Ann Arbor, Michigan, United States
	Javier Zalamea , Josep Llosa , Eduard Ayguadé , Mateo Valero, Software and hardware techniques to optimize register file utilization in VLIW architectures, International Journal of Parallel Programming, v.32 n.6, p.447-474, December 2004
	Rajeev Balasubramonian , Sandhya Dwarkadas , David H. Albonesi, Reducing the complexity of the register file in dynamic superscalar processors, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
	Rama Sangireddy, Register port complexity reduction in wide-issue processors with selective instruction execution, Microprocessors & Microsystems, v.31 n.1, p.51-62, February, 2007
	Albert Meixner , Daniel J. Sorin, Unified microprocessor core storage, Proceedings of the 4th international conference on Computing frontiers, May 07-09, 2007, Ischia, Italy
	J. Adam Butts , Gurindar S. Sohi, Use-Based Register Caching with Decoupled Indexing, ACM SIGARCH Computer Architecture News, v.32 n.2, p.302, March 2004
	Mikko H. Lipasti , Brian R. Mestan , Erika Gunadi, Physical Register Inlining, ACM SIGARCH Computer Architecture News, v.32 n.2, p.325, March 2004
	Saisanthosh Balakrishnan , Gurindar S. Sohi, Exploiting Value Locality in Physical Register Files, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.265, December 03-05, 2003
	Shuai Wang , Hongyan Yang , Jie Hu , Sotirios G. Ziavras, Asymmetrically banked value-aware register files for low-energy and high-performance, Microprocessors & Microsystems, v.32 n.3, p.171-182, May, 2008
	Eric P. Villasenor , DaeHo Seo , Mithuna S. Thottethodi, Power-efficient clustering via incomplete bypassing, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India