Multiple-transform pipelines for image coding

ABSTRACT

Pipelined VLSI/WSI architectures supporting image coding transforms are defined and evaluated in the paper. The structures proposed in the paper have been derived by considering a common algorithmic kernel of the set of examined transforms. The possibility of reducing the computations to a common algorithmic version allows definition of flexible structures characterized by a “basic” pipeline - performing the common kernel of computation - and by transform-dependent input and output stages. Three different pipelines have been defined and figures of merit, such as silicon area occupation and throughput, have been evaluated for architectures comparisons.

REFERENCES

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Performance attributes

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Pipeline processors**
  C.5 COMPUTER SYSTEM IMPLEMENTATION
      C.5.1 Large and Medium ("Mainframe") Computers
          Subjects: Super (very large) computers

  F. Theory of Computation
  F.2 ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY
      F.2.1 Numerical Algorithms and Problems
          Subjects: Computation of transforms (e.g., fast Fourier transform)

General Terms:
Algorithms, Design, Performance