| An intelligent memory system |
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ACM SIGARCH Computer Architecture News
archive
Volume 16 , Issue 4 (September 1988)
table of contents
Special Issue: Architectural Support for Operating Systems
Pages: 12 - 20
Year of Publication: 1988
ISSN:0163-5964
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Authors
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A. Asthana
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AT&T Bell Laboratories, 600 Mountain Ave., Murray Hill, NJ
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H. V. Jagadish
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AT&T Bell Laboratories, 600 Mountain Ave., Murray Hill, NJ
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J. A. Chandross
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AT&T Bell Laboratories, 600 Mountain Ave., Murray Hill, NJ
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D. Lin
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AT&T Bell Laboratories, 600 Mountain Ave., Murray Hill, NJ
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S. C. Knauer
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AT&T Bell Laboratories, 600 Mountain Ave., Murray Hill, NJ
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| Bibliometrics |
Downloads (6 Weeks): 13, Downloads (12 Months): 19, Citation Count: 2
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ABSTRACT
SWIM(Structured Wafer-Scale Intelligent Memory) is a high bandwidth, multi-ported, disk-sized memory system capable of storing, maintaining, and manipulating data structures within it, independent of the main processing units. Up to thousands of active storage elements, each element having some storage and some associated processing logic, function independently or in groups to implement userdefined objects. SWIM increases memory functionality to better balance the time spent in moving data with that involved in actually manipulating it. Just as one may associate a cache with each processor, each memory module has processing logic associated with it. Such logic decreases the processormemory bandwidth requirements, improves memory utilization, scales better in a multiprocessor, and yields a faster response from memory. The faster response results from proximity, a specialized micro architecture and parallelism.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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[2] William R. Smith et al, "SYMBOL - A Large Experimental System Exploring Major Hardware Replacement of Software," in Proceedings of 1971 Joint Computer Conference, vol. 38, AFIPS, 601-616.
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[3] Yaohan Chu, "Evolution of Computer Memory Structure," in Proceedings 1976 National Computer Conference, vol. 45, AFIPS, 733-748.
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[4] P. M. Davies, "Design for an Associative Computer," in Proceedings Pacific Computer Conference, AFIPS, 1963.
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[5] G. Estrin and R. Fuller, "Algorithms for Content Addressable Memory Organizations," in Proceedings 1963 Pacific Computer Conference, vol. 24, AFIPS.
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[6] Richard G. Ewing and Paul M. Davies, "An Associative Processor," in Proceedings of the 1964 Joint Computer Conference, vol. 26, AFIPS.
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[7] W. K. Giloi and H. K. Berg, "STARLET - and Unorthodox Concept of a String/ Array Computer," in Proceedings IFIP Congress, vol. 1, 1974, 103-107.
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[8] J. A. Githens, "A Fully Parallel Computer for Radar Data Processing," Naecon 70 Record, 290-297.
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[9] A. G. Hanlon, "Content-Addressable and Associative Memory Systems - a Survey," IEEE Transactions Electronic Computers, EC-15, 4 (August 1966), 509-521.
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[11] G. Hollander, "Quasi-Random Access Memory Systems," in Proceedings of the Eastern Joint Computer Conference, 1956, 128-135.
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[12] R. N. Ibbett, The Architecture of High Performance Computers, Springer-Verlag, New York, 1982.
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[15] J. Rattner, "Architecture of the Intel iAPX Micromainframe: A Personal History," Lambda, 2, 1 (1981), 27-29.
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[16] Jack A. Rudolph, "A Production Implementation of an Associative Array Processor - STARAN," in Proceedings of the 1972 Fall Joint Computer Conference, vol. 41, AFIPS, 229-241.
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CITED BY 2
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Arun Kejariwal , Alexandru Nicolau , Utpal Banerjee , Alexander V. Veidenbaum , Constantine D. Polychronopoulos, Cache-aware partitioning of multi-dimensional iteration spaces, Proceedings of SYSTOR 2009: The Israeli Experimental Systems Conference, May 04-April 06, 2009, Haifa, Israel
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