| Floorplanning with alignment and performance constraints |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 39th annual Design Automation Conference
table of contents
New Orleans, Louisiana, USA
SESSION: Floorplanning and placement
table of contents
Pages: 848 - 853
Year of Publication: 2002
ISBN ~ ISSN:0738-100X , 1-58113-461-4
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Authors
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Xiaoping Tang
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University of Texas at Austin, Austin, TX, and Silicon Perspective, A Cadence Company, Santa Clara, CA
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D. F. Wong
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University of Texas at Austin, Austin, TX
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Downloads (6 Weeks): 6, Downloads (12 Months): 31, Citation Count: 14
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ABSTRACT
In this paper, we present a floorplanning algorithm based on sequence pair representation. Our floorplanner has the following important features: 1) It is explicitly designed for fixed-frame floorplanning, which is different from traditional well-researched min-area floorplanning. Moreover, we also show that it can be adapted to minimize total area. 2) It addresses the problem of handling alignment constraint which arises in bus structure. 3) It deals with performance constraint such as bounded net delay, while many existing floorplanners just minimize total wire length. 4) More importantly, even with all these constraints the algorithm is very fast in that it evaluates the feasibility of a sequence pair and translates to a floorplan in O(n log log n) time typically where n is the number of blocks and the number of constrained blocks is O(n), which is significantly faster than the O(n3) method operating on constraint graph. Our algorithm is based on computing the longest common subsequence of a pair of weighted sequences. Experimental results on MCNC benchmark for block placement show the promise of the method.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Yun-Chih Chang , Yao-Wen Chang , Guang-Ming Wu , Shu-Wei Wu, B*-Trees: a new representation for non-slicing floorplans, Proceedings of the 37th conference on Design automation, p.458-463, June 05-09, 2000, Los Angeles, California, United States
[doi> 10.1145/337292.337541]
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Pei-Ning Guo , Chung-Kuan Cheng , Takeshi Yoshimura, An O-tree representation of non-slicing floorplan and its applications, Proceedings of the 36th ACM/IEEE conference on Design automation, p.268-273, June 21-25, 1999, New Orleans, Louisiana, United States
[doi> 10.1145/309847.309928]
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Xianlong Hong , Gang Huang , Yici Cai , Jiangchun Gu , Sheqin Dong , Chung Kuan Cheng , Jun Gu, Corner block list: an effective and efficient topological representation of non-slicing floorplan, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
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H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani. "VLSI module placement based on rectangle-packing by the sequence pair", IEEE Transaction on CAD, vol. 15:12, pp. 1518--1524, 1996
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Shigetoshi Nakatake , Kunihiro Fujiyoshi , Hiroshi Murata , Yoji Kajitani, Module placement on BSG-structure and IC layout applications, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.484-491, November 10-14, 1996, San Jose, California, United States
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T. Ohtsuki, N. Sugiyama, and H. Kawanishi. "An optimization technique for integrated circuit layout design", ICCST Kyoto, Japan, pp. 67--68, 1970
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K. Sakanushi and Y. Kajitani. "The quarter-state sequence (Q-sequence) to represent the floorplan and applications to layout optimization", IEEE APCCAS, pp. 829--832, 2000
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Xiaoping Tang , Ruiqi Tian , D. F. Wong, Fast evaluation of sequence pair in block placement by longest common subsequence computation, Proceedings of the conference on Design, automation and test in Europe, p.106-111, March 27-30, 2000, Paris, France
[doi> 10.1145/343647.343713]
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CITED BY 15
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Jingcao Hu , Youngsoo Shin , Nagu Dhanwada , Radu Marculescu, Architecting voltage islands in core-based system-on-a-chip designs, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
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