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Floorplanning with alignment and performance constraints
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 39th annual Design Automation Conference table of contents
New Orleans, Louisiana, USA
SESSION: Floorplanning and placement table of contents
Pages: 848 - 853  
Year of Publication: 2002
ISBN ~ ISSN:0738-100X , 1-58113-461-4
Authors
Xiaoping Tang  University of Texas at Austin, Austin, TX, and Silicon Perspective, A Cadence Company, Santa Clara, CA
D. F. Wong  University of Texas at Austin, Austin, TX
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 6,   Downloads (12 Months): 31,   Citation Count: 14
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ABSTRACT

In this paper, we present a floorplanning algorithm based on sequence pair representation. Our floorplanner has the following important features: 1) It is explicitly designed for fixed-frame floorplanning, which is different from traditional well-researched min-area floorplanning. Moreover, we also show that it can be adapted to minimize total area. 2) It addresses the problem of handling alignment constraint which arises in bus structure. 3) It deals with performance constraint such as bounded net delay, while many existing floorplanners just minimize total wire length. 4) More importantly, even with all these constraints the algorithm is very fast in that it evaluates the feasibility of a sequence pair and translates to a floorplan in O(n log log n) time typically where n is the number of blocks and the number of constrained blocks is O(n), which is significantly faster than the O(n3) method operating on constraint graph. Our algorithm is based on computing the longest common subsequence of a pair of weighted sequences. Experimental results on MCNC benchmark for block placement show the promise of the method.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani. "VLSI module placement based on rectangle-packing by the sequence pair", IEEE Transaction on CAD, vol. 15:12, pp. 1518--1524, 1996
 
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T. Ohtsuki, N. Sugiyama, and H. Kawanishi. "An optimization technique for integrated circuit layout design", ICCST Kyoto, Japan, pp. 67--68, 1970
 
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K. Sakanushi and Y. Kajitani. "The quarter-state sequence (Q-sequence) to represent the floorplan and applications to layout optimization", IEEE APCCAS, pp. 829--832, 2000
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CITED BY  14

Collaborative Colleagues:
Xiaoping Tang: colleagues
D. F. Wong: colleagues