| TCG-S: orthogonal coupling of P*-admissible representations for general floorplans |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 39th annual Design Automation Conference
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New Orleans, Louisiana, USA
SESSION: Floorplanning and placement
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Pages: 842 - 847
Year of Publication: 2002
ISBN ~ ISSN:0738-100X , 1-58113-461-4
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Downloads (6 Weeks): 4, Downloads (12 Months): 16, Citation Count: 10
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ABSTRACT
We extend in this paper the concept of the P-admissible floorplan representation to that of the P*-admissible one. A P*-admissible representation can model the most general floorplans. Each of the currently existing P*-admissible representations, SP, BSG, and TCG, has its strengths as well as weaknesses. We show the equivalence of the two most promising P*-admissible representations, TCG and SP, and integrate TCG with a packing sequence (part of SP) into a new representation, called TCG-S. TCG-S combines the advantages of SP and TCG and at the same time eliminates their disadvantages. With the property of SP, faster packing and perturbation schemes are possible. Inherited nice properties from TCG, the geometric relations among modules are transparent to TCG-S (implying faster convergence to a desired solution), placement with position constraints becomes much easier, and incremental update for cost evaluation can be realized. These nice properties make TCG-S a superior representation which exhibits an elegant solution structure to facilitate the search for a desired floorplan/placement. Extensive experiments show that TCG-S results in the best area utilization, wirelength optimization, convergence speed, and stability among existing works and is very flexible in handling placement with special constraints.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 10
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Hsun-Cheng Lee , Yao-Wen Chang , Jer-Ming Hsu , Hannah H. Yang, Multilevel floorplanning/placement for large-scale modules using B*-trees, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
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Jason Cong , Gabriele Nataneli , Michail Romesis , Joseph R. Shinnerl, An area-optimality study of floorplanning, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
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Catherine Dezan , Ciprian Teodorov , Loïc Lagadec , Michael Leuchtenburg , Teng Wang , Pritish Narayanan , Andras Moritz, Towards a framework for designing applications onto hybrid nano/CMOS fabrics, Microelectronics Journal, v.40 n.4-5, p.656-664, April, 2009
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