CMOS: a paradigm for low power wireless?

ABSTRACT

An overview and comparison of different topologies for wireless architectures are discussed, where the main focus lies on the power consumption and possibilities towards integration and reduction of external components. Architectures with reduced number of building blocks (both internal and external) are presented where the main benefits are the low costs, both in the CMOS technology as well as the power.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

General Terms:
Design

Keywords:
CMOS, low-power, receivers, wireless