Constraint-driven communication synthesis

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Constraint-driven communication synthesis

Full text

Pdf (349 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 39th annual Design Automation Conference table of contents

New Orleans, Louisiana, USA

SESSION: Development of processors and communication networks for embedded systems table of contents

Pages: 783 - 788

Year of Publication: 2002

ISBN ~ ISSN:0738-100X , 1-58113-461-4

Authors

Alessandro Pinto	UC Berkeley, Berkeley, CA
Luca P. Carloni	UC Berkeley, Berkeley, CA
Alberto L. Sangiovanni-Vincentelli	UC Berkeley, Berkeley, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 24, Citation Count: 23

Additional Information:

abstract references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/513918.514114 What is a DOI?

ABSTRACT

Constraint-driven Communication Synthesis enables the automatic design of the communication architecture of a complex system from a library of pre-defined Intellectual Property (IP) components. The key communication parameters that govern all the point-to-point interactions among system modules are captured as a set of arc constraints in the communication constraint graph. Similarly, the communication features offered by each of the components available in the IP communication library are captured as a set of feature resources together with its cost figures. Then, every communication architecture that can be built using the available components while satisfying all constraints is implicitly considered (as an implementation graph matching the constraint graph) to derive the optimum design solution with respect to the desired cost figure. The corresponding constrained optimization problem is efficiently solved by a novel algorithm that is presented here together with its rigorous theoretical foundations.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Luca P. Carloni , Kenneth L. McMillan , Alexander Saldanha , Alberto L. Sangiovanni-Vincentelli, A methodology for correct-by-construction latency insensitive design, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.309-315, November 07-11, 1999, San Jose, California, United States
	2	C. Chang, P. Kermani, and A. Kershenbaum. Multi-link-speed network topology design. In International Phoenix Conference on Computers and Communications, pages 299--306, 1992.
	3	Jean-Marc Daveau , Tarek Ben Ismail , Ahmed Amine Jerraya, Synthesis of system-level communication by an allocation-based approach, Proceedings of the 8th international symposium on System synthesis, p.150-155, September 13-15, 1995, Cannes, France [doi>10.1145/224486.224534]
	4	E. I. Goldberg, L. P. Carloni, T. Villa, R. K. Brayton, and A. L. Sangiovanni-Vincentelli. Negative Thinking in Branch-and-Bound: the Case of Unate Covering. IEEE Transactions on Computer-Aided Design, 19(3):281--294, Mar. 2000.
	5	K. Keutzer, S. Malik, A. R. Newton, J. Rabaey, and A. Sangiovanni-Vincentelli. System level design: Orthogonolization of concerns and platform based design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(12), December 2000.
	6	P. V. Knudsen and J. Madsen. Integrating Communication Protocol Selection with Hardware/Software Codesign. IEEE Transactions on Computer-Aided Design, 18(8):1077--1095, Aug. 1999.
	7	Kanishka Lahiri , Anand Raghunathan , Sujit Dey, Efficient exploration of the SoC communication architecture design space, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	8	Stan Liao , Srinivas Devadas, Solving covering problems using LPR-based lower bounds, Proceedings of the 34th annual conference on Design automation, p.117-120, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266046]
	9	L.-S. Peh and W. J. Dally. Flit reservation flow control. In International Symposium on High-Performance Computer Architecture, pages 74--84, 1999.
	10	A. Pinto, L. P. Carloni, and A. L. Sangiovanni-Vincentelli. Constraint-Driven Communication Synthesis. Technical Report available at www.cad.eecs.berkeley.edu/~lcarloni, Apr. 2002.
	11	Ralph H. J. M. Otten , Robert K. Brayton, Planning for performance, Proceedings of the 35th annual conference on Design automation, p.122-127, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277071]

CITED BY 23

	Alberto L. Sangiovanni-Vincentelli , Alessandro Pinto, An overview of embedded system design education at berkeley, ACM Transactions on Embedded Computing Systems (TECS), v.4 n.3, p.472-499, August 2005
	Alberto Luigi Sangiovanni-Vincentelli , Alessandro Pinto, Embedded system education: a new paradigm for engineering schools?, ACM SIGBED Review, v.2 n.4, p.5-14, October 2005
	Tapani Ahonen , David A. Sigüenza-Tortosa , Hong Bin , Jari Nurmi, Topology optimization for application-specific networks-on-chip, Proceedings of the 2004 international workshop on System level interconnect prediction, February 14-15, 2004, Paris, France
	Sujan Pandey , Manfred Glesner , Max Mühlhäuser, Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture, Proceedings of the 18th annual symposium on Integrated circuits and system design, September 04-07, 2005, Florianolpolis, Brazil
	Krishna Sekar , Kanishka Lahiri , Anand Raghunathan , Sujit Dey, FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Trevor Meyerowitz , Claudio Pinello , Alberto Sangiovanni-Vincentelli, A tool for describing and evaluating hierarchical real-time bus scheduling policies, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Srinivasan Murali , Martijn Coenen , Andrei Radulescu , Kees Goossens , Giovanni De Micheli, Mapping and configuration methods for multi-use-case networks on chips, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Sudeep Pasricha , Nikil Dutt , Elaheh Bozorgzadeh , Mohamed Ben-Romdhane, Floorplan-aware automated synthesis of bus-based communication architectures, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Sudeep Pasricha , Nikil Dutt , Mohamed Ben-Romdhane, Automated throughput-driven synthesis of bus-based communication architectures, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Sujan Pandey , Manfred Glesner, Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Sudeep Pasricha , Nikil D. Dutt , Elaheh Bozorgzadeh , Mohamed Ben-Romdhane, FABSYN: floorplan-aware bus architecture synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.3, p.241-253, March 2006
	Sujan Pandey , Manfred Glesner, Simultaneous on-chip bus synthesis and voltage scaling under random on-chip data traffic, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.10, p.1111-1124, October 2007
	Srinivasan Murali , Martijn Coenen , Andrei Radulescu , Kees Goossens , Giovanni De Micheli, A methodology for mapping multiple use-cases onto networks on chips, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Jiang Xu , Wayne Wolf , Joerg Henkel , Srimat Chakradhar, A design methodology for application-specific networks-on-chip, ACM Transactions on Embedded Computing Systems (TECS), v.5 n.2, p.263-280, May 2006
	Ilya Issenin , Nikil Dutt, Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea
	Alessandro Pinto , Alvise Bonivento , Allberto L. Sangiovanni-Vincentelli , Roberto Passerone , Marco Sgroi, System level design paradigms: Platform-based design and communication synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.3, p.537-563, July 2006
	Sankalp Kallakuri , Alex Doboli , Simona Doboli, Applying stochastic modeling to bus arbitration for systems-on-chip, Integration, the VLSI Journal, v.40 n.2, p.183-191, February, 2007
	Srinivasan Murali , Giovanni De Micheli, An Application-Specific Design Methodology for STbus Crossbar Generation, Proceedings of the conference on Design, Automation and Test in Europe, p.1176-1181, March 07-11, 2005
	Sujan Pandey , Rolf Drechsler, Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Sujan Pandey , Rolf Drechsler, Slack allocation based co-synthesis and optimization of bus and memory architectures for MPSoCs, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Krishna Sekar , Kanishka Lahiri , Anand Raghunathan , Sujit Dey, Dynamically configurable bus topologies for high-performance on-chip communication, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.10, p.1413-1426, October 2008
	M-C. Frank Chang , Jason Cong , Adam Kaplan , Chunyue Liu , Mishali Naik , Jagannath Premkumar , Glenn Reinman , Eran Socher , Sai-Wang Tam, Power reduction of CMP communication networks via RF-interconnects, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.376-387, November 08-12, 2008
	Samar Abdi , Gunar Schirner , Ines Viskic , Hansu Cho , Yonghyun Hwang , Lochi Yu , Daniel Gajski, Hardware-dependent software synthesis for many-core embedded systems, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan