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ABSTRACT
Security protocols are critical to enabling the growth of a wide range of wireless data services and applications. However, they impose a high computational burden that is mismatched with the modest processing capabilities and battery resources available on wireless clients. Bridging the security processing gap, while retaining sufficient programmability in order to support a wide range of current and future security protocol standards, requires the use of novel system architectures and design methodologies.We present the system-level design methodology used to design a programmable security processor platform for next-generation wireless handsets. The platform architecture is based on (i) a configurable and extensible processor that is customized for efficient domain-specific processing, and (ii) layered software libraries implementing cryptographic algorithms that are optimized to the hardware platform. Our system-level design methodology enables the efficient co design of optimal cryptographic algorithms and an optimized system architecture. It includes novel techniques for algorithmic exploration and tuning, performance characterization and macro-modeling of software libraries, and architecture refinement based on selection of instruction extensions to accelerate performance-critical, computation-intensive operations. We have designed a programmable security processor platform to support both public-key and private key operations using the proposed methodology, and have evaluated its performance through extensive system simulations as well as hardware prototyping. Our experiments demonstrate large performance improvements (e.g., 31.0X for DES, 33.9X for 3DES, 17.4X for AES, and upto 66.4X for RSA) compared to well-optimized software implementations on a state-of-the-art embedded processor.
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CITED BY 20
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David Hwang , Bo-Cheng Lai , Patrick Schaumont , Kazuo Sakiyama , Yi Fan , Shenglin Yang , Alireza Hodjat , Ingrid Verbauwhede, Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
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Divya Arora , Anand Raghunathan , Srivaths Ravi , Murugan Sankaradass , Niraj K. Jha , Srimat T. Chakradhar, Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
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Divya Arora , Anand Raghunathan , Srivaths Ravi , Murugan Sankaradass , Niraj K. Jha , Srimat T. Chakradhar, Exploring software partitions for fast security processing on a multiprocessor mobile SoC, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.6, p.699-710, June 2007
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INDEX TERMS
Primary Classification:
C.
Computer Systems Organization
C.0
GENERAL
Additional Classification:
C.
Computer Systems Organization
C.1
PROCESSOR ARCHITECTURES
C.1.0
General
C.2
COMPUTER-COMMUNICATION NETWORKS
C.2.0
General
C.5
COMPUTER SYSTEM IMPLEMENTATION
C.5.3
Microcomputers
Subjects:
Portable devices (e.g., laptops, personal digital assistants)
E.
Data
E.3
DATA ENCRYPTION
Subjects:
Public key cryptosystems
General Terms:
Algorithms,
Design,
Performance,
Security
Keywords:
3DES,
AES,
DES,
IPSec,
RSA,
SSL,
decryption,
design methodology,
embedded system,
encryption,
handset,
performance,
platform,
security,
security processing,
system architecture,
wireless
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