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System design methodologies for a wireless security processing platform
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 39th annual Design Automation Conference table of contents
New Orleans, Louisiana, USA
SESSION: Development of processors and communication networks for embedded systems table of contents
Pages: 777 - 782  
Year of Publication: 2002
ISBN ~ ISSN:0738-100X , 1-58113-461-4
Authors
Srivaths Ravi  NEC USA, Princeton, NJ
Anand Raghunathan  C & C Research Labs, NEC USA, Princeton, NJ
Nachiketh Potlapally  NEC USA, Princeton, NJ
Murugan Sankaradass  NEC USA, Princeton, NJ
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

Security protocols are critical to enabling the growth of a wide range of wireless data services and applications. However, they impose a high computational burden that is mismatched with the modest processing capabilities and battery resources available on wireless clients. Bridging the security processing gap, while retaining sufficient programmability in order to support a wide range of current and future security protocol standards, requires the use of novel system architectures and design methodologies.We present the system-level design methodology used to design a programmable security processor platform for next-generation wireless handsets. The platform architecture is based on (i) a configurable and extensible processor that is customized for efficient domain-specific processing, and (ii) layered software libraries implementing cryptographic algorithms that are optimized to the hardware platform. Our system-level design methodology enables the efficient co design of optimal cryptographic algorithms and an optimized system architecture. It includes novel techniques for algorithmic exploration and tuning, performance characterization and macro-modeling of software libraries, and architecture refinement based on selection of instruction extensions to accelerate performance-critical, computation-intensive operations. We have designed a programmable security processor platform to support both public-key and private key operations using the proposed methodology, and have evaluated its performance through extensive system simulations as well as hardware prototyping. Our experiments demonstrate large performance improvements (e.g., 31.0X for DES, 33.9X for 3DES, 17.4X for AES, and upto 66.4X for RSA) compared to well-optimized software implementations on a state-of-the-art embedded processor.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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CITED BY  20

Collaborative Colleagues:
Srivaths Ravi: colleagues
Anand Raghunathan: colleagues
Nachiketh Potlapally: colleagues
Murugan Sankaradass: colleagues