On the efficacy of simplified 2D on-chip inductance models

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

On the efficacy of simplified 2D on-chip inductance models

Full text

Pdf (211 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 39th annual Design Automation Conference table of contents

New Orleans, Louisiana, USA

SESSION: Inductance and substrate analysis table of contents

Pages: 757 - 762

Year of Publication: 2002

ISBN ~ ISSN:0738-100X , 1-58113-461-4

Authors

Tao Lin	Carnegie Mellon University, Pittsburgh, PA
Michael W. Beattie	Carnegie Mellon University, Pittsburgh, PA
Lawrence T. Pileggi	Carnegie Mellon University, Pittsburgh, PA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 15, Citation Count: 8

Additional Information:

abstract references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/513918.514108 What is a DOI?

ABSTRACT

Full three-dimensional (3D) inductance models of on-chip interconnect contain an extremely large number of forward coupling terms. It is therefore desirable to use a two-dimensional (2D) approximation in which forward couplings are not included. Unlike capacitive coupling, however, truncating mutual inductance terms can result in loss of accuracy and even instability. This paper investigates whether ignoring forward couplings is an acceptable choice for all good IC designs or if full 3D models are necessary in certain on-chip interconnect configurations. We show that the significance of the forward coupling inductance depends on various aspects of the design.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	F. Grover, Inductance Calculations: Working Formulas and Tables, Dover Publications, 1973.
	2	C. Hoer and C. Love, Exact inductance equations for rectangular conductors with applications to more complicated geometries, Journal of Research of the National Bureau of Standards, 69C, No. 2, April-June 1965.
	3	Kaushik Gala , Vladimir Zolotov , Rajendran Panda , Brian Young , Junfeng Wang , David Blaauw, On-chip inductance modeling and analysis, Proceedings of the 37th conference on Design automation, p.63-68, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337313]
	4	Norman Chang , Shen Lin , Lei He , O. Sam Nakagawa , Weize Xie, Clocktree RLC extraction with efficient inductance modeling, Proceedings of the conference on Design, automation and test in Europe, p.522-526, March 27-30, 2000, Paris, France [doi>10.1145/343647.343838]
	5	Min Xu , Lei He, An efficient model for frequency-dependent on-chip inductance, Proceedings of the 11th Great Lakes symposium on VLSI, p.115-120, March 2001, West Lafayette, Indiana, United States [doi>10.1145/368122.368887]
	6	Michael W. Beattie , Lawrence T. Pileggi, Electromagnetic parasitic extraction via a multipole method with hierarchical refinement, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.437-444, November 07-11, 1999, San Jose, California, United States
	7	K. Nabors and J. White, FastCap: A Multipole Accelerated 3D Capacitance Extraction Program, IEEE Trans. CAD, vol. 10, pp. 1447--1459, Nov. 1991.
	8	M. Kamon, M. Tsuk, and J. White, FastHenry: A Multipole Accelerated 3D Inductance Extraction Program, IEEE Trans. Microwave Theory and Techniques, 42, pp. 1750--1758, Sept. 1994.
	9	Raphael Interconnect Analysis Program V98.4 Reference Manual, Avant! Corporation, Nov. 1998.
	10	A. Ruehli, Equivalent Circuit Models for Three-Dimensional Multiconductor Systems", IEEE Trans. Microwave Theory and Techniques, MTT-22, No. 3, pp. 216--221, March 1974.
	11	Byron Krauter , Lawrence T. Pileggi, Generating sparse partial inductance matrices with guaranteed stability, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.45-52, November 05-09, 1995, San Jose, California, United States
	12	Zhijiang He , Mustafa Celik , Lawrence Pileggi, SPIE: sparse partial inductance extraction, Proceedings of the 34th annual conference on Design automation, p.137-140, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266050]
	13	A. J. Dammers , N. P. van der Meijs, Virtual screening: a step towards a sparse partial inductance matrix, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.445-452, November 07-11, 1999, San Jose, California, United States
	14	K. L. Shepard , D. Sitaram , Yu Zheng, Full-chip, three-dimensional, shapes-based RLC extraction, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	15	M. Beattie, et al., Equipotential Shells for Efficient Inductance Extraction, IEEE Trans. CAD, 20, No. 1, pp. 70--79, January 2001.
	16	Anirudh Devgan , Hao Ji , Wayne Dai, How to efficiently capture on-chip inductance effects: introducing a new circuit element K, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	17	M. Beattle , L. Pileggi, Efficient inductance extraction via windowing, Proceedings of the conference on Design, automation and test in Europe, p.430-436, March 2001, Munich, Germany

CITED BY 8

	Jun Chen , Lei He, Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA
	Tao Lin , Lawrence T. Pileggi, Throughput-driven IC communication fabric synthesis, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.274-279, November 10-14, 2002, San Jose, California
	Rafael Escovar , Salvador Ortiz , Roberto Suaya, Mutual inductance extraction and the dipole approximation, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Jitesh Jain , Stephen Cauley , Cheng-Kok Koh , Venkataramanan Balakrishnan, SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Jun Chen , Lei He, Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnects, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Hao Yu , Lei He, Vector potential equivalent circuit based on PEEC inversion, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Sanjay Pant , Eli Chiprout, Power grid physics and implications for CAD, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Hong Li , Venkataramanan Balakrishnan , Cheng-Kok Koh, Stable and compact inductance modeling of 3-D interconnect structures, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California