Towards global routing with RLC crosstalk constraints

ABSTRACT

Conventional global routing minimizes total wire length and congestion. Experiments using large industrial benchmark circuits show that up to 24% of nets in such routing solutions may have RLC crosstalk violations at 3GHz clock. We develop an extremely efficient length-scaled Keff (LSK) model that has a high fidelity for long-range RLC crosstalk. We formulate an extended global routing problem (denoted as GSINO) to consider simultaneous shield insertion and net ordering with RLC crosstalk constraints, then propose an effective three-phase GSINO algorithm. The GSINO algorithm completely eliminates the RLC crosstalk violations, and has small area and wire length overhead compared to conventional routing.

REFERENCES

• 1: T. Xue and E. S. Kuh, "Post global routing crosstalk synthesis," TCAD, pp. 1418--1430, Dec. 1997.
• 2: H. Zhou and D. F. Wong, "Global routing with crosstalk constraints," TCAD, November 1999.
• 3: L. He, N. Chang, S. Lin, and O. S. Nakagawa, "An efficient inductance modeling for on-chip interconnects," in CICC, 1999.
• 4: Lei He , Kevin M. Lepak, Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization, Proceedings of the 2000 international symposium on Physical design, p.55-60, May 2000, San Diego, California, United States [doi>10.1145/332357.332374]
• 5: Guoan Zhong , Cheng Kok Koh , Kaushik Roy, A twisted-bundle layout structure for minimizing inductive coupling noise, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
• 6: Yehia Massoud , Jamil Kawa , Don MacMillen , Jacob White, Modeling and analysis of differential signaling for minimizing inductive cross-talk, Proceedings of the 38th conference on Design automation, p.804-809, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379070]
• 7: J. D. Ma and L. He, "Towards global routing with RLC crosstalk constraints," in University of Wisconsin, Technical Report, ECE-02-1, 2002.
• 8: Arvind Parihar, Pre-Routing Estimation of Shielding for RLC Signal Integrity, Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors, p.553, September 23-26, 2001
• 9: Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 1999.
• 10: Jason Cong , Bryan Preas, A new algorithm for standard cell global routing, Integration, the VLSI Journal, v.14 n.1, p.49-65, Nov. 1992 [doi>10.1016/0167-9260(92)90010-V]
• 11: Maogang Wang , Xiaojian Yang , Majid Sarrafzadeh, Dragon2000: standard-cell placement tool for large industry circuits, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
• 12: James D. Z. Ma , Lei He, Formulae and applications of interconnect estimation considering shield insertion and net ordering, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing

General Terms:
Algorithms, Design, Theory