Compiler-directed scratch pad memory hierarchy design and management

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Compiler-directed scratch pad memory hierarchy design and management

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 39th annual Design Automation Conference table of contents

New Orleans, Louisiana, USA

SESSION: Timing analysis and memory optimization for embedded systems table of contents

Pages: 628 - 633

Year of Publication: 2002

ISBN ~ ISSN:0738-100X , 1-58113-461-4

Authors

M. Kandemir	Pennsylvania State University, University Park, PA
A. Choudhary	Northwestern University, Evanston, IL

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 17, Downloads (12 Months): 68, Citation Count: 30

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

One of the primary challenges in embedded system design is designing the memory hierarchy and restructuring the application to take advantage of it. This task is particularly important for embedded image and video processing applications that make heavy use of large multi-dimensional arrays of signals and nested loops. In this paper, we show that a simple reuse vector/matrix abstraction can provide compiler with useful information in a concise form. Using this information, compiler can either adapt application to an existing memory hierarchy or can come up with a memory hierarchy. Our initial results indicate that the compiler is very successful in both optimizing code for a given memory hierarchy and designing a hierarchy with reasonable performance/size ratio.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	Bernhard Egger , Chihun Kim , Choonki Jang , Yoonsung Nam , Jaejin Lee , Sang Lyul Min, A dynamic code placement technique for scratchpad memory using postpass optimization, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, October 22-25, 2006, Seoul, Korea
	Federico Angiolini , Francesco Menichelli , Alberto Ferrero , Luca Benini , Mauro Olivieri, A post-compiler approach to scratchpad mapping of code, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA
	O. Ozturk , M. Kandemir , I. Demirkiran , G. Chen , M. J. Irwin, Data compression for improving SPM behavior, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	M. Kandemir , O. Ozturk , M. Karakoy, Dynamic on-chip memory management for chip multiprocessors, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA
	Joonseok Park , Pedro C. Diniz , K. R. Shesha Shayee, Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations, IEEE Transactions on Computers, v.53 n.11, p.1420-1435, November 2004
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