| Automatic generation of embedded memory wrapper for multiprocessor SoC |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 39th annual Design Automation Conference
table of contents
New Orleans, Louisiana, USA
SESSION: System on chip design
table of contents
Pages: 596 - 601
Year of Publication: 2002
ISBN ~ ISSN:0738-100X , 1-58113-461-4
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Downloads (6 Weeks): 5, Downloads (12 Months): 30, Citation Count: 16
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 ABSTRACT
Embedded memory plays a critical role to improve performances of systems-on-chip (SoC). In this paper, we present a new methodology for embedded memory design in the case of application specific multiprocessor system-on-chip. This approach facilitates the integration of standard memory components. The concept of memory wrapper allows automatic adaptation of physical memory interfaces to a communication network that may have a different number of access ports. We give also a generic architecture to produce this memory wrapper. This approach has successfully been applied on a low-level image processing application.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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W. Cesário, A. Baghdadi, L. Gauthier, D. Lyonnard, G. Nicolescu, Y. Paviot, S. Yoo, A.A. Jerraya, M. Diaz-Nava "Component-Based Design Approach for Multicore SoCs", DAC 2002
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D.D. Gajski, J. Zhu, R. Dömer, A. Gerstlauer, and S.zhao, "SpecC: Specification Langage and Methodology, Kluwer Academic Publisher., 2000
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Synopsys, Inc., http://www.systemc.org/
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Coware, Inc., http://www.coware.com/cowareN2C.html
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K. Takemura, M. Mizuno, and A. Motohara, "An approach to System-Level Bus Architecture validation and its Application to digital Still Camera Design", Workshop SASIMI, pp. 195--201, Apr. 2000
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J.-Y. Brunel , W. M. Kruijtzer , H. J. H. N. Kenter , F. Pétrot , L. Pasquier , E. A. de Kock , W. J. M. Smits, COSY communication IP's, Proceedings of the 37th conference on Design automation, p.406-409, June 05-09, 2000, Los Angeles, California, United States
[doi> 10.1145/337292.337515]
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Sungjoo Yoo , Gabriela Nicolescu , Damien Lyonnard , Amer Baghdadi , Ahmed A. Jerraya, A generic wrapper architecture for multi-processor SoC cosimulation and design, Proceedings of the ninth international symposium on Hardware/software codesign, p.195-200, April 2001, Copenhagen, Denmark
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Damien Lyonnard , Sungjoo Yoo , Amer Baghdadi , Ahmed A. Jerraya, Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip, Proceedings of the 38th conference on Design automation, p.518-523, June 2001, Las Vegas, Nevada, United States
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Samy Meftali , Ferid Gharsalli , Frederic Rousseau , Ahmed A. Jerraya, An optimal memory allocation for application-specific multiprocessor system-on-chip, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
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CITED BY 16
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JoAnn M. Paul , Alex Bobrek , Jeffrey E. Nelson , Joshua J. Pieper , Donald E. Thomas, Schedulers as model-based design elements in programmable heterogeneous multiprocessors, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
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Férid Gharsalli , Damien Lyonnard , Samy Meftali , Frédéric Rousseau , Ahmed A. Jerraya, Unifying memory and processor wrapper architecture in multiprocessor SoC design, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
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O. Ozturk , M. Kandemir , G. Chen , M. J. Irwin , M. Karakoy, Customized on-chip memories for embedded chip multiprocessors, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
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M. Kandemir , O. Ozturk , M. Karakoy, Dynamic on-chip memory management for chip multiprocessors, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA
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Liping Xue , Ozcan ozturk , Feihui Li , Mahmut Kandemir , I. Kolcu, Dynamic partitioning of processing and memory resources in embedded MPSoC architectures, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
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Andrew S. Cassidy , JoAnn M. Paul , Donald E. Thomas, Layered, Multi-Threaded, High-Level Performance Design, Proceedings of the conference on Design, Automation and Test in Europe, p.10954, March 03-07, 2003
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