False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

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False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 39th annual Design Automation Conference table of contents

New Orleans, Louisiana, USA

SESSION: Advances in timing and simulation table of contents

Pages: 566 - 569

Year of Publication: 2002

ISBN ~ ISSN:0738-100X , 1-58113-461-4

Authors

Jing-Jia Liou	University of California, Santa Barbara, CA
Angela Krstic	University of California, Santa Barbara, CA
Li-C. Wang	University of California, Santa Barbara, CA
Kwang-Ting Cheng	University of California, Santa Barbara, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 9, Downloads (12 Months): 74, Citation Count: 31

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool can characterize statistical circuit delay distribution for the entire circuit and produce a set of true critical paths.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Jing-Jia Liou , Angela Krstic , Kwang-Ting Cheng , Deb Aditya Mukherjee , Sandip Kundu, Performance sensitivity analysis using statistical method and its applications to delay, Proceedings of the 2000 conference on Asia South Pacific design automation, p.587-592, January 2000, Yokohama, Japan [doi>10.1145/368434.368817]
	2	Jing-Jia Liou , Kwang-Ting Cheng , Deb Aditya Mukherjee, Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis, Proceedings of the 18th IEEE VLSI Test Symposium (VTS'00), p.97, April 30-May 04, 2000
	3	Jing-Jia Liou , Kwang-Ting Cheng , Sandip Kundu , Angela Krstic, Fast statistical timing analysis by probabilistic event propagation, Proceedings of the 38th conference on Design automation, p.661-666, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379043]
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CITED BY 31

	Jing-Jia Liou , Li-C. Wang , Angela Krstic , Kwang-Ting Cheng, Experience in critical path selection for deep sub-micron delay test and timing validation, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Jing-Jia Liou , Li-C. Wang , Kwang-Ting Cheng, On theoretical and practical considerations of path selection for delay fault testing, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.94-100, November 10-14, 2002, San Jose, California
	A. Krstic , L.-C. Wang , K.-T. Cheng , J.-J. Liou , T. M. Mak, Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Li-C. Wang , T. M. Mak , Kwang-Ting Cheng , Magdy S. Abadir, On path-based learning and its applications in delay test and diagnosis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Shih-Chieh Chang , Cheng-Tao Hsieh , Kai-Chiang Wu, Re-synthesis for delay variation tolerance, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Kai Yang , Kwang-Ting Cheng , Li-C. Wang, TranGen: a SAT-based ATPG for path-oriented transition faults, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.92-97, January 27-30, 2004, Yokohama, Japan
	Shuji Tsukiyama, Toward stochastic design for digital circuits: statistical static timing analysis, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.762-767, January 27-30, 2004, Yokohama, Japan
	Xiang Lu , Zhuo Li , Wangqi Qiu , D. M. H. Walker , Weiping Shi, Longest path selection for delay test under process variation, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.98-103, January 27-30, 2004, Yokohama, Japan
	Kai Yang , Kwang-Ting Cheng, Efficient identification of multi-cycle false path, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Lizheng Zhang , Weijen Chen , Yuhen Hu , John A. Gubner , Charlie Chung-Ping Chen, Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Lizheng Zhang , Yuhen Hu , Charlie Chung-Ping Chen, Block based statistical timing analysis with extended canonical timing model, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Seiji Kajihara , Masayasu Fukunaga , Xiaoqing Wen , Toshiyuki Maeda , Shuji Hamada , Yasuo Sato, Path delay test compaction with process variation tolerance, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Masayasu Fukunaga , Seiji Kajihara , Xiaoqing Wen , Toshiyuki Maeda , Shuji Hamada , Yasuo Sato, A dynamic test compaction procedure for high-quality path delay testing, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Kai-Chiang Wu , Cheng-Tao Hsieh , Shih-Chieh Chang, Delay variation tolerance for domino circuits, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Jayashree Sridharan , Tom Chen, Modeling multiple input switching of CMOS gates in DSM technology using HDMR, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Lizheng Zhang , Yuhen Hu , Charlie Chung-Ping Chen, Statistical timing analysis with path reconvergence and spatial correlations, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Anand Ramalingam , Gi-Joon Nam , Ashish Kumar Singh , Michael Orshansky , Sani R. Nassif , David Z. Pan, An accurate sparse matrix based framework for statistical static timing analysis, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Kaviraj Chopra , Bo Zhai , David Blaauw , Dennis Sylvester, A new statistical max operation for propagating skewness in statistical timing analysis, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	L. Lee , Li-C Wang , T. M. Mak , Kwang-Ting Cheng, A path-based methodology for post-silicon timing validation, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.713-720, November 07-11, 2004
	Jeng-Liang Tsai , DongHyun Baik , C. C. -P. Chen , K. K. Saluja, A yield improvement methodology using pre- and post-silicon statistical clock scheduling, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.611-618, November 07-11, 2004
	Vikram Iyengar , Jinjun Xiong , Subbayyan Venkatesan , Vladimir Zolotov , David Lackey , Peter Habitz , Chandu Visweswariah, Variation-aware performance verification using at-speed structural test and statistical timing, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Xin Li , Jiayong Le , Mustafa Celik , L. T. Pileggi, Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.844-851, November 06-10, 2005, San Jose, CA
	Anirudh Devgan , Chandramouli Kashyap, Block-based Static Timing Analysis with Uncertainty, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.607, November 09-13, 2003
	Sarvesh Bhardwaj , Sarma B. K. Vrudhula , David Blaauw, "AU: Timing Analysis Under Uncertainty, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.615, November 09-13, 2003
	Hongliang Chang , Sachin S. Sapatnekar, Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.621, November 09-13, 2003
	Puneet Gupta , Andrew B. Kahng, Manufacturing-Aware Physical Design, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.681, November 09-13, 2003
	Angela Krstic , Li-C. Wang , Kwang-Ting Cheng , Jing-Jia Liou , Magdy S. Abadir, Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step, Proceedings of the conference on Design, Automation and Test in Europe, p.10328, March 03-07, 2003
	Lizheng Zhang , Weijen Chen , Yuhen Hu , Charlie Chung-Ping Chen, Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model, Proceedings of the conference on Design, Automation and Test in Europe, p.952-957, March 07-11, 2005
	Li-C. Wang, Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon Validation, Proceedings of the conference on Design, automation and test in Europe, p.10692, February 16-20, 2004
	Ying-Yen Chen , Jing-Jia Liou, Diagnosis framework for locating failed segments of path delay faults, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.6, p.755-765, June 2008
	Vladimir Zolotov , Jinjun Xiong , Hanif Fatemi , Chandu Visweswariah, Statistical path selection for at-speed test, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California