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ABSTRACT

In high-speed network processors, data queueing has to allow real-time memory (de)allocation, buffering, retrieving, and forwarding of incoming data packets. Its implementation must be highly optimized to combine high speed, low power, large data storage, and high memory bandwidth. In this paper, such data queueing is used as case study to demonstrate the effectiveness of a new system-level exploration method for optimizing the memory performance in dynamic memory management. Assuming that a multi-bank memory architecture is used for data storage, the method trades off bank conflicts against memory accesses during real-time memory (de)allocation. It has been applied to the data queueing module of the PRO³ system [8]. Compared with the conventional memory management technique for embedded systems, our exploration method can save up to 90% of the bank conflicts, which allows to improve worst-case memory performance of data queueing operations by 50% too.

REFERENCES

• 1: Traces available in the internet traffic archive. http://ita.ee.lbl.gov/html/traces.html.
• 2: Alan A. Bertossi , Maria Cristina Pinotti, Mappings for Conflict-Free Access of Paths in Elementary Data Structures, Proceedings of the 6th Annual International Conference on Computing and Combinatorics, p.351-361, July 26-28, 2000
• 3: F. Catthoor et al. VLSI Signal Processing, volume VII, chapter Global Communication and Memory Optimizing Transformations for Low Power Signal Processing Systems, p.178--187. IEEE Press, New York, 1994.
• 4: H.J. Chao et al. Design of a generalized priority queue manager for ATM switches. IEEE Journal on Selected Areas in Communications, 15(5):867--880, June 1997.
• 5: A.K. Choudhury and E.L. Hahne. New implementation of multi-priority pushout for shared memory ATM switches. Computer Communications, 19(3):245--256, March 1996.
• 6: V. Firoiu and M. Borden. A study of active queue management for congestion control. Infocom, Tel Aviv, Israel, March 2000.
• 7: Gr. Doumenis , G. Konstantoulakis , G. Korinthios , G. Lykakis , D. Reisis , G. Synnefakis, A Parallel VLSI Video/Communication Controller, Journal of VLSI Signal Processing Systems, v.28 n.3, p.245-257, July 2001 [doi>10.1023/A:1011121709723]
• 8: C. Georgopoulos et al. A protocol processing architecture backing TCP/IP based security applications in high speed networks. Interworking Conference, Bergen, Norway, 2000.
• 9: L.K. John. Data placement schemes to reduce conflicts in interleaved memories. Computer Journal, 43(2):138--151, 2000.
• 10: Mahmut Kandemir , Ugur Sezer , Victor Delaluz, Improving memory energy using access pattern classification, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
• 11: K.A. Khare, P.R. Panda, N.D. Dutt, and A. Nicolau. High-level synthesis with SDRAMs and RAMBUS DRAMs. IEICE Trans. on Fundamentals of Electronics, Communications, and Computer Sciences, 11:2347--2355, 1999.
• 12: V. Kumar, T. Lakshman, and D. Stiliadis. Beyond best effort: Router architectures for the differentiated services of tomorrow's internet. IEEE Communications Magazine, p.152--164, May 1998.
• 13: Micron. http://www.micron.com.
• 14: N. Murphy. Safe memory usage with dynamic allocation. Embedded Systems, p.49--57, May 2000.
• 15: A. Nikologiannis and M. Katevenis. Efficient per-flow queueing in DRAM at OC-192 line rate using out-of-order execution techniques. Int. Conf. On Communications, p.2048--2052, 2001.
• 16: J.L. Rexford, A.G. Greenberg, and F.G. Bonomi. Hardware-efficient fair queueing architectures for high-speed networks. Infocom, p.638--646, March 1996.
• 17: D.N. Serpanos and P. Karakonstantis. Efficient memory management for high speed ATM systems. Design Automation for Embedded Systems, 6(2):207--235, April 2001.
• 18: B. Suter, T.V. Lakshman, D. Stiliadis, and A.K. Choudhury. Buffer management schemes for supporting TCP in gigabit routers with per-flow queueing. IEEE Journal on Selected Areas in Communications, August 1999.
• 19: S. Wuytack et al. Memory management for embedded network applications. IEEE Trans. on CAD, 18(5):533--544, 1999.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.3 Performance Analysis and Design Aids**

General Terms:
Performance

Keywords:
memory management, system-level exploration