Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors

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Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 39th annual Design Automation Conference table of contents

New Orleans, Louisiana, USA

SESSION: Multi-voltage, multi-threshold design table of contents

Pages: 486 - 491

Year of Publication: 2002

ISBN ~ ISSN:0738-100X , 1-58113-461-4

Authors

Tanay Karnik	Intel Labs, Hillsboro, OR
Yibin Ye	Intel Labs, Hillsboro, OR
James Tschanz	Intel Labs, Hillsboro, OR
Liqiong Wei	Intel Labs, Hillsboro, OR
Steven Burns	Intel Labs, Hillsboro, OR
Venkatesh Govindarajulu	Intel Labs, Hillsboro, OR
Vivek De	Intel Labs, Hillsboro, OR
Shekhar Borkar	Intel Labs, Hillsboro, OR

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 36, Citation Count: 25

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ABSTRACT

We describe various design automation solutions for design migration to a dual-Vt process technology. We include the results of a Lagrangian Relaxation based tool, iSTATS, and a heuristic iterative optimization flow. Joint dual-Vt allocation and sizing reduces total power by 10+% compared with Vt allocation alone, and by 25+% compared with pure sizing methods. The heuristic flow requires 5x larger computation runtime than iSTATS due to its iterative nature.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Chen, C.P., Chu, C., and Wong, D.F., Fast and exact simultaneous gate and wire sizing by LR. IEEE TCAD, Vol. 18, No. 7, July 1999, 1014--1025.
	2	Tohru Ishihara , Kunihiro Asada, A system level memory power optimization technique using multiple supply and threshold voltages, Proceedings of the 2001 conference on Asia South Pacific design automation, p.456-461, January 2001, Yokohama, Japan [doi>10.1145/370155.370512]
	3	Uming Ko , Andrew Pua , Anthony Hill , Pranjal Srivastava, Hybrid dual-threshold design techniques for high-performance processors with low-power features, Proceedings of the 1997 international symposium on Low power electronics and design, p.307-311, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263362]
	4	Pankaj Pant , Rabindra K. Roy , Abhijit Chatterjee, Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.2, p.390-394, April 2001 [doi>10.1109/92.924061]
	5	Supamas Sirichotiyakul , Tim Edwards , Chanhee Oh , Jingyan Zuo , Abhijit Dharchoudhury , Rajendran Panda , David Blaauw, Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing, Proceedings of the 36th ACM/IEEE conference on Design automation, p.436-441, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309975]
	6	Vijay Sundararajan , Keshab K. Parhi, Low power synthesis of dual threshold voltage CMOS VLSI circuits, Proceedings of the 1999 international symposium on Low power electronics and design, p.139-144, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313900]
	7	Nikhil Tripathi , Amit Bhosle , Debasis Samanta , Ajit Pal, Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits, Proceedings of the The 14th International Conference on VLSI Design (VLSID '01), p.227, January 03-07, 2001
	8	Liqiong Wei , Zhanping Chen , Kaushik Roy , Mark C. Johnson , Yibin Ye , Vivek K. De, Design and optimization of dual-threshold circuits for low-voltage low-power applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.1, p.16-24, March 1999 [doi>10.1109/92.748196]
	9	Liqiong Wei , Zhanping Chen , Kaushik Roy , Yibin Ye , Vivek De, Mixed-Vth (MVT) CMOS circuit design methodology for low power applications, Proceedings of the 36th ACM/IEEE conference on Design automation, p.430-435, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309974]
	10	Wei, L., Roy, K., and Koh, C. K., Power Minimization by Simultaneous Dual-Vth Assignment and Gate-sizing. IEEE CICC 2000, 413--416.
	11	Qi Wang , Sarma B. K. Vrudhula, Static power optimization of deep submicron CMOS circuits for dual VT technology, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.490-496, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.289076]
	12	An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits, Proceedings of the 1999 IEEE International Conference on Computer Design, p.556, October 10-13, 1999

CITED BY 25

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	Amit Agarwal , Chris H. Kim , Saibal Mukhopadhyay , Kaushik Roy, Leakage in nano-scale technologies: mechanisms, impact and design considerations, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	David Nguyen , Abhijit Davare , Michael Orshansky , David Chinnery , Brandon Thompson , Kurt Keutzer, Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	W. Hung , Y. Xie , N. Vijaykrishnan , M. Kandemir , M. J. Irwin , Y. Tsai, Total power optimization through simultaneously multiple-v_DD multiple-v_TH assignment and device sizing with stack forcing, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Ashish Srivastava , Dennis Sylvester , David Blaauw, Statistical optimization of leakage power considering process variations using dual-Vth and sizing, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Bernd Obermeier , Frank M. Johannes, Temperature-aware global placement, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.143-148, January 27-30, 2004, Yokohama, Japan
	Frank Sill , Frank Grassert , Dirk Timmermann, Low power gate-level design with mixed-V_th (MVT) techniques, Proceedings of the 17th symposium on Integrated circuits and system design, September 07-11, 2004, Pernambuco, Brazil
	Shekhar Borkar , Tanay Karnik , Siva Narendra , Jim Tschanz , Ali Keshavarzi , Vivek De, Parameter variations and impact on circuits and microarchitecture, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Kanak Agarwal , Dennis Sylvester , David Blaauw , Anirudh Devgan, Achieving continuous V_T performance in a dual V_T process, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Tanay Karnik , Shekhar Borkar , Vivek De, Sub-90nm technologies: challenges and opportunities for CAD, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.203-206, November 10-14, 2002, San Jose, California
	Hsinwei Chou , Yu-Hao Wang , Charlie Chung-Ping Chen, Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Bipul C. Paul , Amit Agarwal , Kaushik Roy, Low-power design techniques for scaled technologies, Integration, the VLSI Journal, v.39 n.2, p.64-89, March 2006
	Lara D. Oliver , Krishnendu Chakrabarty , Hisham Z. Massoud, An evaluation of the impact of gate oxide tunneling on dual-V_t-based leakage reduction techniques, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Rupesh S. Shelar, An efficent clustering algorithm for low power clock tree synthesis, Proceedings of the 2007 international symposium on Physical design, March 18-21, 2007, Austin, Texas, USA
	Jeegar Tilak Shah , Marius Evers , Jeff Trull , Alper Halbutogullari, Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors, Proceedings of the 2007 international symposium on Physical design, March 18-21, 2007, Austin, Texas, USA
	Stephen P. Boyd , Seung-Jean Kim , Dinesh D. Patil , Mark A. Horowitz, Digital Circuit Optimization via Geometric Programming, Operations Research, v.53 n.6, p.899-932, November-December 2005
	Simone Medardoni , Davide Bertozzi , Enrico Macii, Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
	Ralf Salomon , Frank Sill , Dirk Timmermann, Minimizing leakage: what if every gate could have its individual threshold voltage?, Proceedings of the 25th conference on Proceedings of the 25th IASTED International Multi-Conference: artificial intelligence and applications, p.492-497, February 12-14, 2007, Innsbruck, Austria
	Ralf Salomon , Frank Sill, High-speed, low-leakage integrated circuits: An evolutionary algorithm perspective, Journal of Systems Architecture: the EUROMICRO Journal, v.53 n.5-6, p.321-327, May, 2007
	Amit Agarwal , Kunhyuk Kang , Swarup Bhunia , James D. Gallagher , Kaushik Roy, Device-aware yield-centric dual-Vt design under parameter variations in nanoscale technologies, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.6, p.660-671, June 2007
	S. Shah , A. Srivastava , D. Sharma , D. Sylvester , D. Blaauw , V. Zolotov, Discrete Vt assignment and gate sizing using a self-snapping continuous formulation, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.705-712, November 06-10, 2005, San Jose, CA
	Jinseob Jeong , Seungwhun Paik , Youngsoo Shin, Statistical mixed V_t allocation of body-biased circuits for reduced leakage variation, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Jaehyun Kim , Youngsoo Shin, Minimizing leakage power in sequential circuits by using mixed V_t flip-flops, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Tai-Hsuan Wu , Lin Xie , Azadeh Davoodi, A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India
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