Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

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Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 39th annual Design Automation Conference table of contents

New Orleans, Louisiana, USA

SESSION: Multi-voltage, multi-threshold design table of contents

Pages: 480 - 485

Year of Publication: 2002

ISBN ~ ISSN:0738-100X , 1-58113-461-4

Authors

Mohab Anis	University of Waterloo, Waterloo, Ontario, Canada
Mohamed Mahmoud	University of Waterloo, Waterloo, Ontario, Canada
Mohamed Elmasry	University of Waterloo, Waterloo, Ontario, Canada
Shawki Areibi	School of Engineering, University of Guelph, Guelph, Ontario, Canada

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 12, Downloads (12 Months): 54, Citation Count: 31

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ABSTRACT

Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. This paper presents two techniques for efficient gate clustering in MTCMOS circuits by modeling the problem via Bin-Packing (BP) and Set-Partitioning (SP) techniques. An automated solution is presented, and both techniques are applied to six benchmarks to verify functionality. Both methodologies offer significant reduction in both dynamic and leakage power over previous techniques during the active and standby modes respectively. Furthermore, the SP technique takes the circuit's routing complexity into consideration which is critical for Deep Sub-Micron (DSM) implementations. Sufficient performance is achieved, while significantly reducing the overall sleep transistors' area. Results obtained indicate that our proposed techniques can achieve on average 90% savings for leakage power and 15% savings for dynamic power.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	Ankur Srivastava, Simultaneous Vt selection and assignment for leakage optimization, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Jason H. Anderson , Farid N. Najm , Tim Tuan, Active leakage power optimization for FPGAs, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Changbo Long , Jinjun Xiong , Lei He, On optimal physical synthesis of sleep transistors, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Changbo Long , Lei He, Distributed sleep transistor network for power reduction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.9, p.937-946, September 2004
	Takeshi Kitahara , Hiroyuki Hara , Shinichiro Shiratake , Yoshiki Tsukiboshi , Tomoyuki Yoda , Tetsuaki Utsumi , Fumihiro Minami, Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Pietro Babighian , Luca Benini , Alberto Macii , Enrico Macii, Post-layout leakage power minimization based on distributed sleep transistor insertion, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Suhwan Kim , Stephen V. Kosonocky , Daniel R. Knebel , Kevin Stawiasz, Experimental measurement of a novel power gating structure with intermediate power saving mode, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Yong-Jun Xu , Zu-Ying Luo , Xiao-Wei Li , Li-Jian Li , Xian-Long Hong, Leakage current estimation of CMOS circuit with stack effect, Journal of Computer Science and Technology, v.19 n.5, p.708-717, September 2004
	Afshin Abdollahi , Farzan Fallah , Massoud Pedram, An effective power mode transition technique in MTCMOS circuits, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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	Behnam Amelifard , Farzan Fallah , Massoud Pedarm, Low-power fanout optimization using MTCMOS and multi-Vt techniques, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany
	Harmander Singh , Kanak Agarwal , Dennis Sylvester , Kevin J. Nowka, Enhanced leakage reduction techniques using intermediate strength power gating, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.11, p.1215-1224, November 2007
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	Pietro Babighian , Luca Benini , Alberto Macii , Enrico Macii, Enabling fine-grain leakage management by voltage anchor insertion, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	A. Sathanur , A. Calimera , L. Benini , A. Macii , E. Macii , M. Poncino, Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	J. H. Anderson , F. N. Najm, Low-power programmable routing circuitry for FPGAs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.602-609, November 07-11, 2004
	Wang Yu , Lin Hai , Yang Huazhong , Luo Rong , Wang Hui, Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization, Proceedings of the 7th International Symposium on Quality Electronic Design, p.723-728, March 27-29, 2006
	Chanseok Hwang , Changwoo Kang , Massoud Pedram, Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs, Proceedings of the 7th International Symposium on Quality Electronic Design, p.741-746, March 27-29, 2006
	Kanak Agarwal , Kevin Nowka , Harmander Deogun , Dennis Sylvester, Power Gating with Multiple Sleep Modes, Proceedings of the 7th International Symposium on Quality Electronic Design, p.633-637, March 27-29, 2006
	Ang-Chih Hsieh , Tzu-Teng Lin , Tsuang-Wei Chang , Tingting Hwang, A functionality-directed clustering technique for low-power MTCMOS design—computation of simultaneously discharging current, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.3, p.1-25, August 2007
	Liangpeng Guo , Yici Cai , Qiang Zhou , Le Kang , Xianlong Hong, A novel performance driven power gating based on distributed sleep transistor network, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
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	Afshin Abdollahi , Farzan Fallah , Massoud Pedram, A robust power gating structure and power mode transition strategy for MTCMOS design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.1, p.80-89, January 2007
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