Low-swing clock domino logic incorporating dual supply and dual threshold voltages

ABSTRACT

High-speed domino logic is now prevailing in performance critical block of a chip. Low Voltage Swing Clock (LVSC) domino logic family is developed for substantial dynamic power saving. To boost up the transition speed in proposed circuitry, a well-established dual threshold voltage technique is exploited. Dual supply voltage technique in the LVSC domino logic is geared to reduce power consumption in clock tree and logic gates effectively. Delay Constrained Power Optimization (DCPO) algorithm allocates low supply voltage to logic gates such that dynamic power consumed by logic gates is minimized. Delay time variations due to gate-to-source voltage change and and input signal arrival time difference are considered for accurate timing analysis in DCPO.

REFERENCES

• 1: Chunhong Chen , Ankur Srivastava , Majid Sarrafzadeh, On gate level power optimization using dual-supply voltages, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.5, p.616-629, October 2001 [doi>10.1109/92.953496]
• 2: Zhanping Chen , Mark Johnson , Liqiong Wei , Kaushik Roy, Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks, Proceedings of the 1998 international symposium on Low power electronics and design, p.239-244, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280917]
• 3: Mutsunori Igarashi , Kimiyoshi Usami , Kazutaka Nogami , Fumihiro Minami , Yukio Kawasaki , Takahiro Aoki , Midori Takano , Chiharo Mizuno , Takashi Ishikawa , Masahiro Kanazawa , Shinji Sonoda , Makoto Ichida , Naoyuki Hatanaka, A low-power design method using multiple supply voltages, Proceedings of the 1997 international symposium on Low power electronics and design, p.36-41, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263279]
• 4: S. M. Kang and Y. Leblebici. CMOS Digital Integrated Circuits: Analysis and Design. McGraw-Hill, 2nd ed., 1999.
• 5: Bharath Ramasubramanian , Herman Schmit , L. Richard Carley, Mixed-swing quadrail for low power dual-rail domino logic, Proceedings of the 1999 international symposium on Low power electronics and design, p.82-84, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313864]
• 6: A. Rjoub, O. Koufopavlou, and S. Nikolaidis. Low power/low swing domino CMOS logic. In Proc. IEEE Int. Symp. Circuits and Systems, pages II.13--II.16, 1998.
• 7: T. Sakurai and A. R. Newton. Alpha-power law mosfet model and its application to CMOS inverter delay and other formulas. IEEE J. Solid State Circuits, 29(6):655--662, June 1994.
• 8: S. J. Shieh and J. S. Wang. Design of low-power domino circuits using multiple supply voltages. In Proc. IEEE Int. Conf. Electronics, Circuits and Systems, pages 711--714, 2001.
• 9: Y. J. Yeh, S. Y. Kuo, and J. Y. Jou. Converter free multiple scaling techniques for low-power CMOS digital design. IEEE Trans. Computer-Aided Design, 20(1):172--176, Jan. 2001.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

General Terms:
Design

Keywords:
domino logic, dual supply voltage, dual threshold voltage, low power, low swing clock