Power estimation in global interconnects and its reduction using a novel repeater optimization methodology

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Power estimation in global interconnects and its reduction using a novel repeater optimization methodology

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 39th annual Design Automation Conference table of contents

New Orleans, Louisiana, USA

SESSION: Low-power physical design table of contents

Pages: 461 - 466

Year of Publication: 2002

ISBN ~ ISSN:0738-100X , 1-58113-461-4

Authors

Pawan Kapur	CIS, Stanford, CA
Gaurav Chandra	CIS, Stanford, CA
Krishna C. Saraswat	CIS, Stanford, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 6, Downloads (12 Months): 42, Citation Count: 22

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ABSTRACT

The purpose of this work is two fold. First, to quantify and establish future trends for the dynamic power dissipation in global wires of high performance integrated circuits. Second, to develop a novel and efficient delay-power tradeoff formulation for minimizing power due to repeaters, which can otherwise constitute 50% of total global wire power dissipation. Using the closed form solutions from this formulation, power savings of 50% on repeaters are shown with minimal delay penalties of about 5% at the 50 nm technology node. These closed-form, analytical solutions provide a fast and powerful tool for designers to minimize power.

REFERENCES

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	Rupesh S. Shelar , Prashant Saxena , Xinning Wang , Sachin S. Sapatnekar, An efficient technology mapping algorithm targeting routing congestion under delay constraints, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
	Yuantao Peng , Xun Liu, Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Yuantao Peng , Xun Liu, A sensitivity analysis of low-power repeater insertion, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Seongmoo Heo , Krste Asanović, Replacing global wires with an on-chip network: a power analysis, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Lin Zhong , Niraj K. Jha, Interconnect-aware high-level synthesis for low power, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.110-117, November 10-14, 2002, San Jose, California
	Quming Zhou , Kartik Mohanram, Elmore model for energy estimation in RC trees, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Guoqing Chen , Eby G. Friedman, Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.2, p.161-172, February 2006
	Yuantao Peng , Xun Liu, Low-power repeater insertion with both delay and slew rate constraints, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Alexandru Andrei , Petru Eles , Zebo Peng , Marcus T. Schmitz , Bashir M. Al Hashimi, Energy optimization of multiprocessor systems on chip by voltage selection, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.3, p.262-275, March 2007
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	V. Chandra , H. Schmit , A. Xu , L. Pileggi, A power aware system level interconnect design methodology for latency-insensitive systems, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.275-282, November 07-11, 2004
	A. Andrei , M. Schmitz , P. Eles , Z. Peng , B. M. Al Hashimi, Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.362-369, November 07-11, 2004
	W.-L. Hung , G. M. Link , Yuan Xie , N. Vijaykrishnan , M. J. Irwin, Interconnect and Thermal-aware Floorplanning for 3D Microprocessors, Proceedings of the 7th International Symposium on Quality Electronic Design, p.98-104, March 27-29, 2006
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	Weiping Liao , Lei He, Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.574, November 09-13, 2003
	Himanshu Kaul , Dennis Sylvester , David Blaauw , Trevor Mudge , Todd Austin, DVS for On-Chip Bus Designs Based on Timing Error Correction, Proceedings of the conference on Design, Automation and Test in Europe, p.80-85, March 07-11, 2005
	Xun Liu , Yuantao Peng , Marios C. Papaefthymiou, RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power, Proceedings of the conference on Design, Automation and Test in Europe, p.1330-1335, March 07-11, 2005
	Jeonghwan Choi , Chen-Yong Cher , Hubertus Franke , Henrdrik Hamann , Alan Weger , Pradip Bose, Thermal-aware task scheduling at the system software level, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
	Ja Chun Ku , Yehea Ismail, Thermal-aware methodology for repeater insertion in low-power VLSI circuits, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
	Ja Chun Ku , Yehea Ismail, Thermal-aware methodology for repeater insertion in low-power VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.8, p.963-970, August 2007