Remembrance of circuits past

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Remembrance of circuits past: macromodeling by data mining in large analog design spaces

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 39th annual Design Automation Conference table of contents

New Orleans, Louisiana, USA

SESSION: Analog synthesis & design methodology table of contents

Pages: 437 - 442

Year of Publication: 2002

ISBN ~ ISSN:0738-100X , 1-58113-461-4

Authors

Hongzhou Liu	Carnegie Mellon University, Pittsburgh, PA
Amit Singhee	Carnegie Mellon University, Pittsburgh, PA
Rob A. Rutenbar	Carnegie Mellon University, Pittsburgh, PA
L. Richard Carley	Carnegie Mellon University, Pittsburgh, PA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 21, Citation Count: 29

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

The introduction of simulation-based analog synthesis tools creates a new challenge for analog modeling. These tools routinely visit 103 to 105 fully simulated circuit solution candidates. What might we do with all this circuit data? We show how to adapt recent ideas from large-scale data mining to build models that capture significant regions of this visited performance space, parameterized by variables manipulated by synthesis, trained by the data points visited during synthesis. Experimental results show that we can automatically build useful nonlinear regression models for large analog design spaces.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	F. De Bernardinis , M. I. Jordan , A. Sangiovanni Vincentelli, Support vector machines for analog circuit performance representation, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Yang Xu , Lawrence T. Pileggi , Stephen P. Boyd, ORACLE: optimization with recourse of analog circuits including layout extraction, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
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	Jian Wang , Jun Tao , Xuan Zeng , Charles Chiang , Dian Zhou, Analog circuit behavioral modeling via wavelet collocation method with auto-companding, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.45-50, January 27-30, 2004, Yokohama, Japan
	Alberto Sangiovanni-Vincentelli , Luca Carloni , Fernando De Bernardinis , Marco Sgroi, Benefits and challenges for platform-based design, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Gang Zhang , Aykut Dengi , Ronald A. Rohrer , Rob A. Rutenbar , L. Richard Carley, A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Anuradha Agarwal , Glenn Wolfe , Ranga Vemuri, Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
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	Mengmeng Ding , Glenn Wolfe , Ranga Vemuri, An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Daniel Mueller , Guido Stehr , Helmut Graeb , Ulf Schlichtmann, Deterministic approaches to analog performance space exploration (PSE), Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	F. De Bernardinis , P. Nuzzo , A. Sangiovanni Vincentelli, Mixed signal design space exploration through analog platforms, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Saurabh K. Tiwary , Pragati K. Tiwary , Rob A. Rutenbar, Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Jun Tao , Xuan Zeng , Dian Zhou , Charles Chiang, Analog behavioral modeling by multi-companding and wavelet collocation method, Analog Integrated Circuits and Signal Processing, v.49 n.3, p.291-297, December 2006
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	R. Vemuri , G. Wolfe, Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.931-938, November 07-11, 2004
	B. Bond , L. Daniel, Parameterized model order reduction of nonlinear dynamical systems, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.487-494, November 06-10, 2005, San Jose, CA
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