Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems

ABSTRACT

Several approaches have been proposed for the syntax-directed compilation of asynchronous circuits from high-level specification languages, such as Balsa and Tangram. Both compilers have been successfully used in large real-world applications; however, in practice, these methods suffer from significant performance overheads due to their reliance on straightforward syntax-directed translation.This paper introduces a powerful new set of transformations, and an extended channel-based language to support them, which can be used an optimizing back-end for Balsa. The transforms described in this paper fall into two categories: resynthesis and peephole. The proposed optimization techniques have been fully integrated into a comprehensive asynchronous CAD package, Balsa. Experimental results on several substantial design examples indicate significant performance improvements. supported by NSF ITR Award No. NSF-CCR-0086036 and NSF Award No. CCR-99-88241, and by a grant from the New York State Microelectronics Design Center.

REFERENCES

• 1: Andrew Bardsley , Doug Edwards, Compiling the language Balsa to delay insensitive hardware, Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems, p.89-91, August 1997, Toledo, Spain
• 2: A. Bardsley, "Implementing Balsa Handshake Circuits", PhD. Thesis, Department of Computer Science, University of Manchester, 2000. BardsleyPersonal A. Bardsley, Personal Communication, 2000.
• 3: E. Brunvand, "Translating Concurrent Communicating Programs into Asynchronous Circuits", Technical Report CMU-CS-91-198, Carnegie Mellon University, 1991.
• 4: T. Chelcea , S. Nowick , A. Bardsley , D. Edwards, A Burst-Mode Oriented Back-End for the Balsa Synthesis System, Proceedings of the conference on Design, automation and test in Europe, p.330, March 04-08, 2002
• 5: Tilman Kolks , Steven Vercauteren , Bill Lin, Control Resynthesis for Control-Dominated Asynchronous Designs, Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems, p.233, March 18-21, 1996
• 6: Robert M. Fuhrer , Steven Nowick, Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools, Kluwer Academic Publishers, Norwell, MA, 2001
• 7: Alain J. Martin, Programming in VLSI: from communicating processes to delay-insensitive circuits, Developments in concurrency and communication, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1991
• 8: Steven M Nowick, Automatic Synthesis of Burst-Mode Asynchronous Controllers, Stanford University, Stanford, CA, 1995
• 9: A.M.G. Peeters, "Single--Rail Handshake Circuits", PhD. Thesis, Department of Computer Science, Technical University of Eindhoven, 1996.
• 10: Marco A. Pena , Jordi Cortadella, Combining Process Algebras and Petri Nets for the Specification and Synthesis of Asynchronous Circuits, Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems, p.222, March 18-21, 1996
• 11: L.A. Plana and S.M. Nowick, "Architectural Optimization for Low-Power Nonpipelined Asynchronous Systems", IEEE Transactions on Very Large Scale Integration Systems, Vol. 6, No. 1, March 1998.
• 12: K. van Berkel, "Handshake Circuits: an Intermediary between Communicating Processes and VLSI", PhD. Thesis, Department of Computer Science, Technical University of Eindhoven, 1992.
• 13: Kees van Berkel, Handshake circuits: an asynchronous architecture for VLSI programming, Cambridge University Press, New York, NY, 1993
• 14: K. van Berkel, Personal Communication, 1999.