Enhancing test efficiency for delay fault testing using multiple-clocked schemes

ABSTRACT

In conventional delay testing, the test clock is a single pre-defined parameter that is often set to be the same as the system clock. This paper discusses the potential of enhancing test efficiency by using multiple clock frequencies. The intuition behind our work is that for a given set of AC delay patterns, a carefully-selected, tighter clock would result in higher effectiveness to screen out the potential defective chips. Then, by using a smarter test clock scheme and combining with a second set of AC delay patterns, the overall quality of AC delay test can be enhanced while the cost of including the second pattern set can be minimized. We demonstrate these concepts through analysis and experiments using a statistical timing analysis framework with defect-injected simulation.

REFERENCES

• 1: Keith Baker , Guido Gronthoud , Maurice Lousberg , Ivo Schanstra , Charles Hawkins, Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation, Proceedings of the 1999 IEEE International Test Conference, p.467, September 28-30, 1999
• 2: M. A. Breuer, C. Gleason, and S. Gupta. New Validation and Test Problems for High Performance Deep Sub-Micron VLSI Circuits. Tutorial Notes, IEEE VLSI Test Symposium, April 1997.
• 3: Jing-Jia Liou , Kwang-Ting Cheng , Deb Aditya Mukherjee, Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis, Proceedings of the 18th IEEE VLSI Test Symposium (VTS'00), p.97, April 30-May 04, 2000
• 4: Jing-Jia Liou , Angela Krstic , Kwang-Ting Cheng , Deb Aditya Mukherjee , Sandip Kundu, Performance sensitivity analysis using statistical method and its applications to delay, Proceedings of the 2000 conference on Asia South Pacific design automation, p.587-592, January 2000, Yokohama, Japan [doi>10.1145/368434.368817]
• 5: Wei-Wei Mao , Michael D. Ciletti, A variable observation time method for testing delay faults, Proceedings of the 27th ACM/IEEE conference on Design automation, p.728-731, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123454]
• 6: V. S. Iyengar and G. Vijayan. Optimized Test Application Timing for AC Test. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(11):1439--1449, November 1992.
• 7: D. Dumas, P. Girard, C. Landrault, and S. Pravossoudovitch. Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. Proceedings of European Design and Test Conference, pages 518--523, March 1994.
• 8: W. B. Jone , Y. P. Ho , S. R. Das, Delay Fault Coverage Enhancement Using Variable Observation Times, Journal of Electronic Testing: Theory and Applications, v.11 n.2, p.131-146, Oct. 1997 [doi>10.1023/A:1008266305694]
• 9: Anacad. Eldo v4.4.x User's Manual. 1996.
• 10: Nandakumar N. Tendolkar, Analysis of timing failures due to random AC defects in VLSI modules, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.709-714, June 1985, Las Vegas, Nevada, United States [doi>10.1145/317825.317967]
• 11: J. P. de~Gyvez. Integrated Circuits Defect-Sensitivity: Theory and Computational Models. Kluwer Academic Publishers, Boston, MA, 1993.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Experimentation, Measurement, Reliability

Keywords:
delay testing, statistical timing analysis, transition fault model