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On output response compression in the presence of unknown output values
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 39th annual Design Automation Conference table of contents
New Orleans, Louisiana, USA
SESSION: Novel DFT, BIST and diagnosis techniques table of contents
Pages: 255 - 258  
Year of Publication: 2002
ISBN ~ ISSN:0738-100X , 1-58113-461-4
Authors
Irith Pomeranz  Purdue University, W. Lafayette, IN
Sandip Kundu  Intel Corp., Austin, TX
Sudhakar M. Reddy  University of Iowa, Iowa City, IA
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 3,   Downloads (12 Months): 10,   Citation Count: 11
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ABSTRACT

A circuit may produce unknown output values during simulation of an input sequence due to an unknown initial state or due to the existence of tri-state elements. For circuits tested using BIST, unknown output values make it impossible to determine a single unique signature for the fault free circuit. To accommodate unknown output values in a BIST scheme, we describe a procedure for synthesizing a minimal logic block that replaces unknown output values by a known constant. The proposed procedure ensures that the BIST scheme will be able to detect all the faults detectable by the input sequence applied to the circuit while allowing a single unique signature to be obtained.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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G. Eide, "Embedded Deterministic Test - DFT Technology for Low-Cost IC Manufacturing Test", www.mentor.com/dft.
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CITED BY  11

Collaborative Colleagues:
Irith Pomeranz: colleagues
Sandip Kundu: colleagues
Sudhakar M. Reddy: colleagues