Low-cost sequential ATPG with clock-control DFT

ABSTRACT

We present a new clock-control DFT tech¿nique for sequential circuits, based on clock partitioning and selective clock freezing, and we use it to break the glo¿bal feedback loops and to generate clock waves to test the resulting sequential circuit with self-loops. Clock waves allow us to significantly reduce the complexity of sequen¿tial ATPG. Unlike scan, our non-intrusive DFT technique does not introduce any delay penalty; the generated tests may be applied at speed, have shorter application time, and dissipate less power.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Algorithms, Design, Reliability