| Carbon nanotube field-effect transistors and logic circuits |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 39th annual Design Automation Conference
table of contents
New Orleans, Louisiana, USA
SESSION: Life after CMOS: Imminent or Irrelevant?
table of contents
Pages: 94 - 98
Year of Publication: 2002
ISBN ~ ISSN:0738-100X , 1-58113-461-4
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Authors
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R. Martel
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IBM T. J. Watson Research Center, Yorktown Heights, NY
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V. Derycke
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IBM T. J. Watson Research Center, Yorktown Heights, NY
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J. Appenzeller
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IBM T. J. Watson Research Center, Yorktown Heights, NY
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S. Wind
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IBM T. J. Watson Research Center, Yorktown Heights, NY
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Ph. Avouris
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IBM T. J. Watson Research Center, Yorktown Heights, NY
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| Bibliometrics |
Downloads (6 Weeks): 23, Downloads (12 Months): 148, Citation Count: 6
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ABSTRACT
In this paper, we present recent advances in the understanding of the properties of semiconducting single wall carbon nanotube and in the exploration of their use as field-effect transistors (FETs). Both electrons and holes can be injected in a nanotube transistor by either controlling the metal-nanotube Schottky barriers present at the contacts or simply by doping the bulk of the nanotube. These methods give complementary nanotube FETs that can be integrated together to make inter- and intra-nanotube logic circuits. The device performance and their general characteristics suggest that they can compete with silicon MOSFETs. While this is true when considering simple prototype devices, several issues remain to be explored before a nanotube-based technology is possible. They are also discussed.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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V. Derycke, R. Martel, J. Appenzeller and Ph. Avouris, Nanoletters 1, 453 (2001).
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A. Bachtold et al., Science 294, 1317 (2001).
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J. Appenzeller, et al. Appl. Phys. Lett. 78, 3313 (2001); C. T. White and T. 10. N. Todorov, Nature (London) 393, 240 (1998).
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J. Appenzeller et al. submitted.
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S. Wind et al., Appl. Phys. Lett., in press.
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T. Ghani et al. Proceedings of IEDM p.215 (1999).
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CITED BY 6
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Margarida Jacome , Chen He , Gustavo de Veciana , Stephen Bijansky, Defect tolerant probabilistic design paradigm for nanotechnologies, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
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INDEX TERMS
Primary Classification:
B.
Hardware
B.6
LOGIC DESIGN
B.6.0
General
General Terms:
Design,
Experimentation,
Measurement,
Performance
Keywords:
FET,
SWNT,
Schottky barrier,
carbon nanotube,
circuits,
field-effect transistor,
inverter,
logic gate,
nanoelectronics,
semiconductor
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