Life is CMOS

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Life is CMOS: why chase the life after?

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 39th annual Design Automation Conference table of contents

New Orleans, Louisiana, USA

SESSION: Life after CMOS: Imminent or Irrelevant? table of contents

Pages: 78 - 83

Year of Publication: 2002

ISBN ~ ISSN:0738-100X , 1-58113-461-4

Authors

George Sery	Intel Corporation, Santa Clara, CA
Shekhar Borkar	Intel Corporation, Santa Clara, CA
Vivek De	Intel Corporation, Santa Clara, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 56, Citation Count: 13

Additional Information:

abstract references cited by index terms collaborative colleagues

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ABSTRACT

This paper discusses potential solutions to the CMOS device technology scaling at gate lengths approaching 10nm. Promising circuit and design techniques to control leakage power are described. Energy-efficient microarchitecture trends for general-purpose microprocessors are elucidated.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R. Chau et al., "30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays", IEDM 2000, pp. 45--48.
	2	R. Chau, "30nm and 20nm Physical Gate Length CMOS Transistors", Silicon Nanotechnology Workshop, 2001.
	3	R. Chau et al., "A 50nm depleted-substrate CMOS transistor (DST)", IEDM 2001, pp. 621--624.
	4	Fred Pollack; New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies; Micro32, 1999.

CITED BY 13

	Shekhar Borkar , Tanay Karnik , Siva Narendra , Jim Tschanz , Ali Keshavarzi , Vivek De, Parameter variations and impact on circuits and microarchitecture, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Swarup Bhunia , Nilanjan Banerjee , Qikai Chen , Hamid Mahmoodi , Kaushik Roy, A novel synthesis approach for active leakage power reduction using dynamic supply gating, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Kanak Agarwal , Dennis Sylvester , David Blaauw , Anirudh Devgan, Achieving continuous V_T performance in a dual V_T process, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Dongwoo Lee , David Blaauw , Dennis Sylvester, Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Tanay Karnik , Shekhar Borkar , Vivek De, Sub-90nm technologies: challenges and opportunities for CAD, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.203-206, November 10-14, 2002, San Jose, California
	Kiran Puttaswamy , Gabriel H. Loh, Thermal analysis of a 3D die-stacked high-performance microprocessor, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Arijit Raychowdhury , Kaushik Roy, Nanometer scale technologies: device considerations, Nano, quantum and molecular computing: implications to high level design and validation, Kluwer Academic Publishers, Norwell, MA, 2004
	Shekhar Borkar, Electronics beyond nano-scale CMOS, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Chinnakrishnan Ballapuram , Kiran Puttaswamy , Gabriel H. Loh , Hsien-Hsin S. Lee, Entropy-based low power data TLB design, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, October 22-25, 2006, Seoul, Korea
	Nam Sung Kim , Taeho Kgil , K. Bowman , V. De , T. Mudge, Total power-optimal pipelining and parallel processing under process variations in nanometer technology, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.535-540, November 06-10, 2005, San Jose, CA
	Praveen Kalla , Xiaobo Sharon Hu , Jörg Henkel, LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction Caches, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.518, November 09-13, 2003
	Bill Grundmann , Rajesh Galivanche , Sandip Kundu, Circuit and Platform Design Challenges in Technologies beyond 90nm, Proceedings of the conference on Design, Automation and Test in Europe, p.10044, March 03-07, 2003
	Zhiyu Liu , Volkan Kursun, Characterization of a novel nine-transistor SRAM cell, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.4, p.488-492, April 2008