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A universal technique for fast and flexible instruction-set architecture simulation
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 39th annual Design Automation Conference table of contents
New Orleans, Louisiana, USA
SESSION: Design innovations for embedded processors table of contents
Pages: 22 - 27  
Year of Publication: 2002
ISBN ~ ISSN:0738-100X , 1-58113-461-4
Authors
Achim Nohl  Integrated Signal Processing Systems, Aachen, Germany
Gunnar Braun  Integrated Signal Processing Systems, Aachen, Germany
Oliver Schliebusch  Integrated Signal Processing Systems, Aachen, Germany
Rainer Leupers  Integrated Signal Processing Systems, Aachen, Germany
Heinrich Meyr  Integrated Signal Processing Systems, Aachen, Germany
Andreas Hoffmann  LISATek Inc., Menlo Park, CA
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 9,   Downloads (12 Months): 95,   Citation Count: 45
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ABSTRACT

In the last decade, instruction-set simulators have become an essential development tool for the design of new programmable architectures. Consequently, the simulator performance is a key factor for the overall design efficiency. Based on the extremely poor performance of commonly used interpretive simulators, research work on fast compiled instruction-set simulation was started ten years ago. However, due to the restrictiveness of the compiled technique, it has not been able to push through in commercial products. This paper presents a new retargetable simulation technique which combines the performance of traditional compiled simulators with the flexibility of interpretive simulation. This technique is not limited to any class of architectures or applications and can be utilized from architecture exploration up to end-user software development. The work-flow and the applicability of the so-called just-in-time cache compiled simulation (JIT-CCS) technique will be demonstrated by means of state of the art real world architectures.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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A. Hoffmann and T. Kogel and A. Nohl and G. Braun and O. Schliebusch and A. Wieferink and H. Meyr. A Novel Methodology for the Design of Application Specific Instruction Set Processors (ASIP) Using a Machine Description Language. IEEE Transactions on Computer-Aided Design, 20(11):1338--1354, 2001.
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E. Schnarr and M.D. Hill and J.R. Larus. Facile: A Language and Compiler For High-Performance Processor Simulators. In Proc. of the Int. Conf. on Programming Language Design and Implementation, 1998.
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C. Mills, S. Ahalt, and J. Fowler. Compiled instruction set simulation. Software - Practice and Experience, 21(8):877--889, 1991.
 
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R. Leupers, J. Elste, and B. Landwehr. Generation of interpretive and compiled instruction set simulators. In Proc. of the Asia South Pacific Design Automation Conference, 1999.

CITED BY  45

Collaborative Colleagues:
Achim Nohl: colleagues
Gunnar Braun: colleagues
Oliver Schliebusch: colleagues
Rainer Leupers: colleagues
Heinrich Meyr: colleagues
Andreas Hoffmann: colleagues