| A simulation-based cost modeling methodology for evaluation of interbay material handling in a semiconductor wafer fab |
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Winter Simulation Conference
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Proceedings of the 32nd conference on Winter simulation
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Orlando, Florida
SESSION: Semiconductor manufacturing
table of contents
Pages: 1510 - 1517
Year of Publication: 2000
ISBN:0-7803-6582-8
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Downloads (6 Weeks): 5, Downloads (12 Months): 27, Citation Count: 2
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ABSTRACT
In the next generation of semiconductor wafer fabrication facilities, decisions concerning material handling systems will be a major factor in initial facility cost, operational cost, production cycle times, and possibly product yield percentages. The wafers will increase in diameter to 300 mm and a new front opening unified pod (FOUP) has been designed to carry them, both increasing the weight of a production lot. This increase requires substantial automation for ergonomic and quality reasons. As a result, semiconductor manufacturers are asking, "What level of automation is financially justifiable?"Automation suppliers have stated that automation saves money, but have as yet not produced a sufficiently detailed financial analysis proving their premise. In this paper, both a fully automated and a manual material handling system are simulated and compared in a thorough cost analysis. Sensitivity analysis is performed on inflation rate, interest rate, die price, wafer start rate, and yield percentage to validate the results of the analyses.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Cardarelli, G. and P. M. Pelagagge, 1995. Simulation tool for designed and management optimization of automated interbay material handling and storage systems for large wafer fab. IEEE Transactions on Semiconductor Manufacturing 8 (1): 44-49.
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Colvin, Theron and Gerald Mackulak, 1999. Fab design and development methodology much change to allow for successful integration of all systems. Semiconductor Fabtech 10: 155-166.
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Fowler, J. W., Brown, S. W., Gold, H., Schoemig, A., "Measurable Improvements in Cycle-Time Constrained Capacity", Proceedings of the Sixth International Symposium on Semiconductor Manufacturing, San Francisco, CA, pp. A21-A24, 1997.
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Weiss, Mitchell, 1999. New twists on fab design and layout. Semiconductor International (July): 103-108.
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Wright, Williams and Kelley, 1995. User Manual, Factory Explorer Version 2.7. Pleasanton, CA: Wright Williams and Kelly.
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Yang, Taho and Brett A. Peters, 1997. A spine layo9ut design method for semiconductor fabrication facilities containing automated material-handling systems. International Journal of Operations & Production Management 17 (5): 490-501.
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