General simulation applications in semiconductor manufacturing: why do simple wafer fab models fail in certain scenarios?

ABSTRACT

Previous work has proved that simple simulation models are sufficient for analyzing the behavior of complex wafer fabs in certain scenarios. In this paper, we give an example where the simple model fails to accurately predict cycle times and WIP levels of the complex model. To determine the reason for this behavior, we analyze the correlation properties of a MIMAC full fab model and the corresponding simple one. It turns out that the simple model is not capable of capturing the correlations in an adequate way because there is lot overtaking (passing) in the simple model while almost no overtaking can be found in the complex counterpart.

REFERENCES

• 1: Fowler, J. and J. Robinson. 1995. Measurement and improvement of manufacturing capacities (MIMAC): Final report. Technical Report 95062861A-TR, SE-MATECH, Austin, TX.
• 2: Dan Gusfield, Algorithms on strings, trees, and sequences: computer science and computational biology, Cambridge University Press, New York, NY, 1997
• 3: Hopp, W. J. and M. L. Spearman. 1991. Throughput of a constant work in process manufacturing line subject to failures. International Journal of Production Research, 29(3):635-655.
• 4: David W. Kelton , Randall P. Sadowski , Deborah A. Sadowski, Simulation with Arena, McGraw-Hill, Inc., New York, NY, 1997
• 5: Averill M. Law , W. David Kelton, Simulation Modeling and Analysis, McGraw-Hill Higher Education, 1997
• 6: William H. Press , Saul A. Teukolsky , William T. Vetterling , Brian P. Flannery, Numerical recipes in C (2nd ed.): the art of scientific computing, Cambridge University Press, New York, NY, 1992
• 7: Oliver Rose, WIP evolution of a semiconductor factory after a bottleneck workcenter breakdown, Proceedings of the 30th conference on Winter simulation, p.997-1004, December 13-16, 1998, Washington, D.C., United States
• 8: Rose, O. 1999a. Estimation of the cycle time distribution of a wafer fab by a simple simulation model. In Proceedings of the SMOMS '99 (1999 WMC).
• 9: Oliver Rose, CONLOAD—a new lot release rule for semiconductor wafer fabs, Proceedings of the 31st conference on Winter simulation: Simulation---a bridge to the future, p.850-855, December 05-08, 1999, Phoenix, Arizona, United States [doi>10.1145/324138.324535]
• 10: Wein, L. M. 1988. Scheduling semiconductor wafer fabrication. IEEE Transactions on Semiconductor Manufacturing, 1(3):115-130.
• 11: Wright Williams & Kelly. 1997. Factory Explorer 2.3 User Manual.