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Reconfigurable computing: a survey of systems and software
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Source ACM Computing Surveys (CSUR) archive
Volume 34 ,  Issue 2  (June 2002) table of contents
Pages: 171 - 210  
Year of Publication: 2002
ISSN:0360-0300
Authors
Katherine Compton  Northwestern University
Scott Hauck  University of Washington
Publisher
ACM  New York, NY, USA
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ABSTRACT

Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this survey, we explore the hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling. We also focus on the software that targets these machines, such as compilation tools that map high-level algorithms directly to the reconfigurable substrate. Finally, we consider the issues involved in run-time reconfigurable systems, which reuse the configurable hardware during program execution.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Abouzeid, P., Babba, P., De Paulet, M. C., and Saucier, G. 1993. Input-driven partitioning methods and application to synthesis on table-lookup-based FPGA's. IEEE Trans. Comput. Aid. Des. Integ. Circ. Syst. 12, 7, 913--925.
 
2
S. J. B. Acock , Keith R. Dimond, Automatic mapping of algorithms onto multiple FPGA-SRAM modules, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.255-264, September 01-03, 1997
 
3
Adaptive Silicon, Inc. 2001. MSA 2500 Programmable Logic Cores. Adaptive Silicon, Inc., Los Gatos, CA.
 
4
Agarwal, A. 1995. VirtualWires: A Technology for Massive Multi-FPGA Systems. Available online at http://www.ikos.com/products/virtual-wires.ps.
 
5
Aditya A. Aggarwal , David M. Lewis, Routing Architectures for Hierarchical Field Programmable Gate Arrays, Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, p.475-478, October 10-12, 1994
 
6
Alexander, M. J. and Robins, G. 1996. New performance-driven FPGA routing algorithms. IEEE Trans. CAD Integ. Circ. Syst. 15, 12, 1505--1517.
 
7
Altera Corporation. 1998. Data Book. Altera Corporation, San Jose, CA.
 
8
Altera Corporation. 1999. Altera MegaCore Functions. Available online at http://www.altera.com/html/tools/megacore.html. Altera Corporation, San Jose, CA.
 
9
Altera Corporation. 2001. Press Release: Altera Unveils First Complete System-on-a-Programmable-Chip Solution at Embedded Systems Conference. Altera Corporation, San Jose, CA.
 
10
Annapolis Microsystems, Inc. 1998. Wildfire Reference Manual. Annapolis Microsystems, Inc, Annapolis, MD.
11
Jeffrey M. Arnold , Duncan A. Buell , Elaine G. Davis, Splash 2, Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures, p.316-322, June 29-July 01, 1992, San Diego, California, United States  [doi>10.1145/140901.141896]
 
12
Jonathan Babb , Martin Rinard , Csaba Andras Moritz , Walter Lee , Matthew Frank , Rajeev Barua , Saman Amarasinghe, Parallelizing Applications into Silicon, Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.70, April 21-23, 1999
 
13
Babb, J., Tessier, R., and Agarwal, A. 1993. Virtual wires: Overcoming pin limitations in FPGA-based logic emulators. In IEEE Workshop on FPGAs for Custom Computing Machines, 142--151.
 
14
P. Bellows , B. Hutchings, JHDL - An HDL for Reconfigurable Systems, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.175, April 15-17, 1998
 
15
Vaughn Betz , Jonathan Rose, VPR: A new packing, placement and routing tool for FPGA research, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.213-222, September 01-03, 1997
16
Vaughn Betz , Jonathan Rose, FPGA routing architecture: segmentation and buffering to optimize speed and density, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.59-68, February 21-23, 1999, Monterey, California, United States  [doi>10.1145/296399.296428]
 
17
Brasen, D. R., and Saucier, G. 1998. Using cone structures for circuit partitioning into FPGA packages. IEEE Trans. CAD Integ. Circ. Syst. 17, 7, 592--600.
 
18
Stephen D. Brown , Robert J. Francis , Jonathan Rose , Zvonko G. Vranesic, Field-programmable gate arrays, Kluwer Academic Publishers, Norwell, MA, 1992
 
19
Brown, S., Rose, J., and Vranesic, Z. G. 1992b. A detailed router for field-programmable gate arrays. IEEE Trans. Comput. Aid. Desi. 11, 5, 620--628.
20
Mihai Budiu , Seth Copen Goldstein, Fast compilation for pipelined reconfigurable fabrics, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.195-205, February 21-23, 1999, Monterey, California, United States  [doi>10.1145/296399.296459]
 
21
Buell, D., Arnold, S. M., and Kleinfelder, W. J. 1996. SPLASH 2: FPGAs in a Custom Computing Machine, IEEE Computer Society Press, Los Alamitos, CA.
 
22
J. Burns , A. Donlin , J. Hogg , S. Singh , M. De Wit, A dynamic reconfiguration run-time system, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.66, April 16-18, 1997
 
23
Butts, M. and Batcheller, J. 1991. Method of using electronically reconfigurable logic circuits. US Patent 5,036,473.
 
24
Srihari Cadambi , Seth Copen Goldstein, CPR: A Configuration Profiling Tool, Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.104, April 21-23, 1999
25
Srihari Cadambi , Jeffrey Weener , Seth Copen Goldstein , Herman Schmit , Donald E. Thomas, Managing pipeline-reconfigurable FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.55-64, February 22-25, 1998, Monterey, California, United States  [doi>10.1145/275107.275120]
26
Timothy J. Callahan , Philip Chong , André DeHon , John Wawrzynek, Fast module mapping and placement for datapaths in FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.123-132, February 22-25, 1998, Monterey, California, United States  [doi>10.1145/275107.275132]
 
27
Timothy J. Callahan , John R. Hauser , John Wawrzynek, The Garp Architecture and C Compiler, Computer, v.33 n.4, p.62-69, April 2000  [doi>10.1109/2.839323]
 
28
Joco M. P. Cardoso , Horacio C. Neto, Macro-Based Hardware Compilation of Java(tm) Bytecodes into a Dynamic Reconfigurable Computing System, Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.2, April 21-23, 1999
 
29
Chameleon Systems, Inc. 2000. CS2000 Advance Product Specification. Chameleon Systems, Inc., San Jose, CA.
 
30
P. K. Chan , M. D. F. Schlag, Acceleration of an FPGA router, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.175, April 16-18, 1997
31
Douglas Chang , Malgorzata Marek-Sadowska, Partitioning sequential circuits on dynamically reconfiguable FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.161-167, February 22-25, 1998, Monterey, California, United States  [doi>10.1145/275107.275136]
 
32
Chang, S. C., Marek-Sadowska, M., and Hwang, T. T. 1996. Technology mapping for TLU FPGA's based on decomposition of binary decision diagrams. IEEE Trans. CAD Integ. Circ. Syst. 15, 10, 1226--1248.
 
33
Anton V. Chichkov , Carlos Beltrán Almeida, A hardware/software partitioning algorithm for custom computing machines, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.274-283, September 01-03, 1997
 
34
Andrew A. Chien , Jay H. Byun, Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor, Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.209, April 21-23, 1999
 
35
Paul Chow , Jonathan Rose , Soon Ong Seo , Kevin Chung , Gerard Páez-Monzón , Immanuel Rahardja, The design of an SRAM-based field-programmable gate array—part I: architecture, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.2, p.191-197, June 1999  [doi>10.1109/92.766746]
 
36
Paul Chow , Soon Ong Seo , Jonathan Rose , Kevin Chung , Gerard Páez-Monzón , Immanuel Rahardja, The design of a SRAM-based field-programmable gate array—part II: circuit design and layout, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.3, p.321-330, Sept. 1999  [doi>10.1109/92.784093]
37
Amit Chowdhary , John P. Hayes, General modeling and technology-mapping technique for LUT-based FPGAs, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.43-49, February 09-11, 1997, Monterey, California, United States  [doi>10.1145/258305.258311]
 
38
M. Chu , N. Weaver , K. Sulimma , A. DeHon , J. Wawrzynek, Object Oriented Circuit-Generators in Java, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.158, April 15-17, 1998
 
39
Compton, K., Cooley, J., Knol, S., and Hauck, S. 2000. Configuration relocation and defragmentation for FPGAs, Northwestern University Technical Report, Available online at http://www.ece.nwu.edu/~kati/publications.html.
 
40
Katherine Compton , Zhiyuan Li , James Cooley , Stephen Knol , Scott Hauck, Configuration relocation and defragmentation for run-time reconfigurable computing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.209-220, June 2002  [doi>10.1109/TVLSI.2002.1043324]
41
Jason Cong , Yean-Yow Hwang, Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.27-34, February 22-25, 1998, Monterey, California, United States  [doi>10.1145/275107.275116]
 
42
Cong, J. and Wu, C. 1998. An efficient algorithm for performance-optimal FPGA technology mapping with retiming. IEEE Trans. CAD Integr. Circ. Syst. 17, 9, 738--748.
43
Jason Cong , Chang Wu , Yuzheng Ding, Cut ranking and pruning: enabling a general and efficient FPGA mapping solution, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.29-35, February 21-23, 1999, Monterey, California, United States  [doi>10.1145/296399.296425]
44
Jason Cong , Songjie Xu, Technology mapping for FPGAs with embedded memory blocks, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.179-188, February 22-25, 1998, Monterey, California, United States  [doi>10.1145/275107.275138]
 
45
D. C. Cronquist , P. Franklin , S. G. Berg , C. Ebeling, Specifying and Compiling Applications for RaPiD, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.116, April 15-17, 1998
46
Andreas Dandalis , Viktor K. Prasanna, Configuration compression for FPGA-based embedded systems, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.173-182, February 2001, Monterey, California, United States  [doi>10.1145/360276.360342]
47
André DeHon, DPGA utilization and application, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, p.115-121, February 11-13, 1996, Monterey, California, United States  [doi>10.1145/228370.228387]
48
André DeHon, Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization), Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.69-78, February 21-23, 1999, Monterey, California, United States  [doi>10.1145/296399.296431]
49
Deepali Deshpande , Arun K. Somani , Akhilish Tyagi, Configuration caching vs data caching for striped FPGAs, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.206-214, February 21-23, 1999, Monterey, California, United States  [doi>10.1145/296399.296461]
 
50
Oliver Diessel , Hossam A. ElGindy, Run-time compaction of FPGA designs, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.131-140, September 01-03, 1997
 
51
Apostolos Dollas , Euripides Sotiriades , Apostolos Emmanouelides, Architecture and Design of GE1, a FCCM for Golomb Ruler Derivation, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.48, April 15-17, 1998
 
52
Carl Ebeling , Darren C. Cronquist , Paul Franklin, RaPiD - Reconfigurable Pipelined Datapath, Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, p.126-135, September 23-25, 1996
53
Abdel Ejnioui , N. Ranganathan, Multi-terminal net routing for partial crossbar-based multi-FPGA systems, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.176-185, February 21-23, 1999, Monterey, California, United States  [doi>10.1145/296399.296454]
54
A. J. Elbirt , C. Paar, An FPGA implementation and performance evaluation of the Serpent block cipher, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.33-40, February 10-11, 2000, Monterey, California, United States  [doi>10.1145/329166.329176]
55
John M. Emmert , Dinesh Bhatia, A methodology for fast FPGA floorplanning, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.47-56, February 21-23, 1999, Monterey, California, United States  [doi>10.1145/296399.296427]
 
56
Estrin, G., Bussel, B., Turn, R., and Bibb, J. 1963. Parallel processing in a restructurable computer system. IEEE Trans. Elect. Comput. 747--755.
 
57
D. Galloway, The Transmogrifier C hardware description language and compiler for FPGAs, Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines, p.136, April 19-21, 1995
 
58
Stephan W. Gehring , Stefan H.-M. Ludwig, The Trianus System and Its Application to Custom Computing, Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, p.176-184, September 23-25, 1996
59
Stephan W. Gehring , Stefan H.-M. Ludwig, Fast integrated tools for circuit design with FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.133-139, February 22-25, 1998, Monterey, California, United States  [doi>10.1145/275107.275133]
 
60
Maya B. Gokhale , Janice M. Stone, NAPA C: Compiling for a Hybrid RISC/FPGA Architecture, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.126, April 15-17, 1998
 
61
Maya B. Gokhale , Janice M. Stone, Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory Banks, Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.63, April 21-23, 1999
 
62
Seth Copen Goldstein , Herman Schmit , Mihai Budiu , Srihari Cadambi , Matt Moe , R. Reed Taylor, PipeRench: A Reconfigurable Architecture and Compiler, Computer, v.33 n.4, p.70-77, April 2000  [doi>10.1109/2.839324]
 
63
Graham, P. and Nelson, B. 1996. Genetic algorithms in software and in hardware---A performance analysis of workstations and custom computing machine implementations. IEEE Symposium on FPGAs for Custom Computing Machines, 216--225.
 
64
Scott Alan Hauck, Multi-FPGA systems, University of Washington, Seattle, WA, 1996
65
Scott Hauck, Configuration prefetch for single context reconfigurable coprocessors, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.65-74, February 22-25, 1998, Monterey, California, United States  [doi>10.1145/275107.275121]
 
66
Hauck, S. 1998b. The roles of FPGAs in reprogrammable systems. Proc. IEEE 86, 4, 615--638.
 
67
Hauck, S. and Agarwal A. 1996. Software technologies for reconfigurable systems. Dept. of ECE Technical Report, Northwestern Univ. Available online at http://www.ee.washington.edu/faculty/hauck/publications.html.
 
68
Hauck, S. and Borriello, G. 1997. Pin assignment for multi-FPGA systems. IEEE Trans. Comput. Aid. Desi. Integ. Circ. Syst. 16, 9, 956--964.
 
69
Hauck, S., Borriello, G., and Ebeling, C. 1998a. Mesh routing topologies for multi-FPGA systems. IEEE Trans. VLSI Syst. 6, 3, 400--408.
 
70
S. Hauck , T. W. Fry , M. M. Hosler , J. P. Kao, The Chimaera reconfigurable functional unit, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.87, April 16-18, 1997
 
71
Scott Hauck , Zhiyuan Li , Eric Schwabe, Configuration Compression for the Xilinx XC6200 FPGA, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.138, April 15-17, 1998
 
72
Hauck, S. and Wilson, W. D. 1999. Runlength compression techniques for FPGA configurations. Dept. of ECE Technical Report, Northwestern Univ. Available online at http://www.ee.washington.edu/faculty/hauck/publications. html.
 
73
J. R. Hauser , J. Wawrzynek, Garp: a MIPS processor with a reconfigurable coprocessor, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.12, April 16-18, 1997
 
74
Simon D. Haynes , Peter Y. K. Cheung, A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.226, April 15-17, 1998
75
Frank Heile , Andrew Leaver, Hybrid product term and LUT based architectures using embedded memory blocks, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.13-16, February 21-23, 1999, Monterey, California, United States  [doi>10.1145/296399.296415]
 
76
Wei-Je Huang , Nirmal Saxena , Edward J. McCluskey, A Reliable LZ Data Compressor on Reconfigurable Coprocessors, Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, p.249, April 17-19, 2000
77
Lorenz Huelsbergen, A representation for dynamic graphs in reconfigurable hardware and its application to fundamental graph algorithms, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.105-115, February 10-11, 2000, Monterey, California, United States  [doi>10.1145/329166.329190]
 
78
Brad Hutchings, Exploiting reconfigurability through domain-specific systems, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.193-202, September 01-03, 1997
 
79
Brad Hutchings , Peter Bellows , Joseph Hawkins , Scott Hemmert , Brent Nelson , Mike Rytting, A CAD Suite for High-Performance FPGA Design, Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.12, April 21-23, 1999
 
80
Hwang, T. T., Owens, R. M., Irwin, M. J., and Wang, K. H. 1994. Logic synthesis for field-programmable gate arrays. IEEE Trans. Comput. Aid. Des. Integ. Circ. Syst. 13, 10, 1280--1287.
 
81
Maurice Kilavuka Inuani , Jonathan Saul, Technology mapping of heterogeneous LUT-based FPGAs, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.223-234, September 01-03, 1997
82
Jeffrey A. Jacob , Paul Chow, Memory interfacing and instruction specification for reconfigurable processors, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.145-154, February 21-23, 1999, Monterey, California, United States  [doi>10.1145/296399.296446]
 
83
Jack S. N. Jean , Karen Tomko , Vikram Yavagal , Jignesh Shah , Robert Cook, Dynamic Reconfiguration to Support Concurrent Applications, IEEE Transactions on Computers, v.48 n.6, p.591-602, June 1999  [doi>10.1109/12.773796]
 
84
Bernardo Kastrup , Arjan Bink , Jan Hoogerbrugge, ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator, Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.92, April 21-23, 1999
 
85
Khalid, M. A. S. 1999. Routing architecture and layout synthesis for multi-FPGA systems. Ph.D. dissertation, Dept. of ECE, Univ. Toronto.
86
Mohammed A. S. Khalid , Jonathan Rose, A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.45-54, February 22-25, 1998, Monterey, California, United States  [doi>10.1145/275107.275119]
87
Hea Joung Kim , William H. Mangione-Smith, Factoring large numbers with programmable hardware, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.41-48, February 10-11, 2000, Monterey, California, United States  [doi>10.1145/329166.329177]
88
Hue-Sung Kim , Arun K. Somani , Akhilesh Tyagi, A reconfigurable multi-function computing cache architecture, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.85-94, February 10-11, 2000, Monterey, California, United States  [doi>10.1145/329166.329185]
 
89
Rainer Kress , Reiner W. Hartenstein , Ulrich Nageldinger, An operating system for custom computing machines based on the Xputer paradigm, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.304-313, September 01-03, 1997
90
H. Krupnova , C. Rabedaoro , G. Saucier, Synthesis and floorplanning for large hierarchical FPGAs, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.105-111, February 09-11, 1997, Monterey, California, United States  [doi>10.1145/258305.258320]
 
91
Yen-Tai Lai , Ping-Tsung Wang, Hierarchical interconnection structures for field programmable gate arrays, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.5 n.2, p.186-196, June 1997  [doi>10.1109/92.585219]
 
92
Ronald Laufer , R. Reed Taylor , Herman Schmit, PCI-PipeRench and the SWORDAPI: A System for Stream-Based Reconfigurable Computing, Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.200, April 21-23, 1999
 
93
Lee, Y. S. and Wu, A. C. H. 1997. A performance and routability-driven router for FPGA's considering path delays. IEEE Trans. CAD Integ. Circ. Syst. 16, 2, 179--185.
 
94
Jason Leonard , William H. Mangione-Smith, A case study of partially evaluated hardware circuits: Key-specific DES, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.151-160, September 01-03, 1997
 
95
K. H. Leung , K. W. Ma , W. K. Wong , P. H. W. Leong, FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor, Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, p.68, April 17-19, 2000
96
David M. Lewis , David R. Galloway , Marcus van Ierssel , Jonathan Rose , Paul Chow, The Transmogrifier-2: a 1 million gate rapid prototyping system, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.53-61, February 09-11, 1997, Monterey, California, United States  [doi>10.1145/258305.258312]
97
Yanbing Li , Tim Callahan , Ervan Darnell , Randolph Harr , Uday Kurkure , Jon Stockwood, Hardware-software co-design of embedded reconfigurable architectures, Proceedings of the 37th conference on Design automation, p.507-512, June 05-09, 2000, Los Angeles, California, United States  [doi>10.1145/337292.337559]
 
98
Zhiyuan Li , Katherine Compton , Scott Hauck, Configuration Caching Management Techniques for Reconfigurable Computing, Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, p.22, April 17-19, 2000
99
Zhiyuan Li , Scott Hauck, Don't Care discovery for FPGA configuration compression, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.91-98, February 21-23, 1999, Monterey, California, United States  [doi>10.1145/296399.296435]
 
100
Xiaochun Lin , Erik L. Dagless , Aiguo Lu, Technology mapping of LUT based FPGAs for delay optimisation, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.245-254, September 01-03, 1997
101
Huiqun Liu , D. F. Wong, Circuit partitioning for dynamically reconfigurable FPGAs, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.187-194, February 21-23, 1999, Monterey, California, United States  [doi>10.1145/296399.296456]
 
102
Lucent Technologies, Inc. 1998. FPGA Data Book. Lucent Technologies, Inc., Allentown, PA.
 
103
W. Luk , N. Shirazi , P. Y. K. Cheung, Compilation tools for run-time reconfigurable designs, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.56, April 16-18, 1997
 
104
Wayne Luk , Nabeel Shirazi , S. R. Guo , Peter Y. K. Cheung, Pipeline morphing and virtual pipelines, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.111-120, September 01-03, 1997
 
105
Patrick Lysaght , Jon Stockwood, A simulation tool for dynamically reconfigurable field programmable gate arrays, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.4 n.3, p.381-390, Sept. 1996  [doi>10.1109/92.532038]
106
Wai-Kei Mak , D. F. Wong, Board-level multiterminal net routing for FPGA-based logic emulation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.2, p.151-167, April 1997  [doi>10.1145/253052.253136]
 
107
Mangione-Smith, W. H. 1999. ATR from UCLA. Personal Commun.
 
108
William H. Mangione-Smith , Brad Hutchings , David Andrews , André DeHon , Carl Ebeling , Reiner Hartenstein , Oskar Mencer , John Morris , Krishna Palem , Viktor K. Prasanna , Henk A. E. Spaanenburg, Seeking Solutions in Configurable Computing, Computer, v.30 n.12, p.38-43, December 1997  [doi>10.1109/2.642810]
109
Alan Marshall , Tony Stansfield , Igor Kostarnov , Jean Vuillemin , Brad Hutchings, A reconfigurable arithmetic array for multimedia applications, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.135-143, February 21-23, 1999, Monterey, California, United States  [doi>10.1145/296399.296444]
 
110
Nicholas McKay , Satnam Singh, Debugging Techniques for Dynamically Reconfigurable Hardware, Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.114, April 21-23, 1999
111
Larry McMurchie , Carl Ebeling, PathFinder: a negotiation-based performance-driven router for FPGAs, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.111-117, February 12-14, 1995, Monterey, California, United States  [doi>10.1145/201310.201328]
 
112
Oskar Mencer , Martin Morf , Michael J. Flynn, PAM-Blox: High Performance FPGA Design for Adaptive Computing, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.167, April 15-17, 1998
 
113
Takashi Miyamori , Kunle Olukotun, A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.2, April 15-17, 1998
 
114
C. A. Moritz , D. Yeung , A. Agarwal, Exploring Optimal Cost-Performance Designs for Raw Microprocessors, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.12, April 15-17, 1998
115
Gi-Joon Nam , Karem A. Sakallah , Rob A. Rutenbar, Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based Boolean SAT, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.167-175, February 21-23, 1999, Monterey, California, United States  [doi>10.1145/296399.296450]
116
Peichen Pan , Chih-Chang Lin, A new retiming-based technology mapping algorithm for LUT-based FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.35-42, February 22-25, 1998, Monterey, California, United States  [doi>10.1145/275107.275118]
 
117
Rob Payne, Run-time parameterised circuits for the Xilinx XC6200, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.161-172, September 01-03, 1997
 
118
Karthikeya M. Gajjala Purna , Dinesh Bhatia, Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers, IEEE Transactions on Computers, v.48 n.6, p.579-590, June 1999  [doi>10.1109/12.773795]
 
119
Quickturn, A Cadence Company. 1999a. System RealizerTM. Available online at http://www.quickturn.com/products/systemrealizer.htm. Quickturn, A Cadence Company, San Jose, CA.
 
120
Quickturn, A Cadence Company. 1999b. MercuryTM Design Verification System Technology Backgrounder. Available online at http://www.quickturn.com/products/mercury_backgrounder.htm. Quickturn, A Cadence Company, San Jose, CA, 1999.
121
Rahul Razdan , Michael D. Smith, A high-performance microarchitecture with hardware-programmable functional units, Proceedings of the 27th annual international symposium on Microarchitecture, p.172-180, November 30-December 02, 1994, San Jose, California, United States  [doi>10.1145/192724.192749]
 
122
M. Rencher , B. L. Hutchings, Automated target recognition on SPLASH 2, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.192, April 16-18, 1997
 
123
Rose, J., El Gamal, A., and Sangiovanni-Vincentelli, A. 1993. Architecture of field-programmable gate arrays. Proc. IEEE 81, 7, 1013--1029.
 
124
C. R. Rupp , M. Landguth , T. Garverick , E. Gomersall , H. Holt , J. M. Arnold , M. Gokhale, The NAPA Adaptive Processing Architecture, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.28, April 15-17, 1998
 
125
Sangiovanni-Vincentelli, A., El Gamal, A., and Rose, J. 1993. Synthesis methods for field programmable gate arrays. Proc. IEEE 81, 7, 1057--1083.
126
Yaska Sankar , Jonathan Rose, Trading quality for compile time: ultra-fast placement for FPGAs, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.157-166, February 21-23, 1999, Monterey, California, United States  [doi>10.1145/296399.296449]
 
127
S. M. Scalera , J. R. Vázquez, The Design and Implementation of a Context Switching FPGA, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.78, April 15-17, 1998
128
Charles Selvidge , Anant Agarwal , Matt Dahl , Jonathan Babb, TIERS: Topology independent pipelined routing and scheduling for VirtualWire compilation, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.25-31, February 12-14, 1995, Monterey, California, United States  [doi>10.1145/201310.201314]
129
S. A. Senouci , A. Amoura , H. Krupnova , G. Saucier, Timing driven floorplanning on programmable hierarchical targets, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.85-92, February 22-25, 1998, Monterey, California, United States  [doi>10.1145/275107.275123]
130
K. Shahookar , P. Mazumder, VLSI cell placement techniques, ACM Computing Surveys (CSUR), v.23 n.2, p.143-220, June 1991  [doi>10.1145/103724.103725]
131
Jianzhong Shi , Dinesh Bhatia, Performance driven floorplanning for FPGA based designs, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.112-118, February 09-11, 1997, Monterey, California, United States  [doi>10.1145/258305.258321]
 
132
N. Shirazi , W. Luk , P. Y. K. Cheung, Automating Production of Run-Time Reconfigurable Designs, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.147, April 15-17, 1998
 
133
Slimane-Kadi, M., Brasen, D., and Saucier, G. 1994. A fast-FPGA prototyping system that uses inexpensive high-performance FPIC. ACM/SIGDA Workshop on Field-Programmable Gate Arrays.
 
134
Euripides Sotiriades , Apostolos Dollas , Peter Athanas, Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation Engine, Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, p.227, April 17-19, 2000
 
135
Jörn Stohmann , Erich Barke, A Universal CLA Adder Generator for SRAM-Based FPGAs, Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, p.44-54, September 23-25, 1996
136
Jordan S. Swartz , Vaughn Betz , Jonathan Rose, A fast routability-driven router for FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.140-149, February 22-25, 1998, Monterey, California, United States  [doi>10.1145/275107.275134]
 
137
Synopsys, Inc. 2000. CoCentric System C Compiler. Synopsys, Inc., Mountain View, CA.
 
138
Synplicity, Inc. 1999. Synplify User Guide Release 5.1. Synplicity, Inc., Sunnyvale, CA.
139
Atsushi Takahara , Toshiaki Miyazaki , Takahiro Murooka , Masaru Katayama , Kazuhiro Hayashi , Akihiro Tsutsui , Takaki Ichimori , Ken-nosuke Fukami, More wires and fewer LUTs: a design methodology for FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.12-19, February 22-25, 1998, Monterey, California, United States  [doi>10.1145/275107.275113]
 
140
Thakur, S., Chang, Y. W., Wong, D. F., and Muthukrishnan, S. 1997. Algorithms for an FPGA switch module routing problem with application to global routing. IEEE Trans. CAD Integ. Circ. Syst. 16, 1, 32--46.
 
141
Togawa, N., Yanagisawa, M., and Ohtsuki, T. 1998. Maple-OPT: A performance-oriented simultaneous technology mapping, placement, and global gouting algorithm for FPGA's. IEEE Trans. CAD Integ. Circ. Syst. 17, 9, 803--818.
142
Steve Trimberger, Scheduling designs into a time-multiplexed FPGA, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.153-160, February 22-25, 1998, Monterey, California, United States  [doi>10.1145/275107.275135]
 
143
S. Trimberger , D. Carberry , A. Johnson , J. Wong, A time-multiplexed FPGA, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.22, April 16-18, 1997
144
Steve Trimberger , Khue Duong , Bob Conn, Architecture issues and solutions for a high-capacity FPGA, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.3-9, February 09-11, 1997, Monterey, California, United States  [doi>10.1145/258305.258306]
145
William Tsu , Kip Macy , Atul Joshi , Randy Huang , Norman Walker , Tony Tung , Omid Rowhani , Varghese George , John Wawrzynek , André DeHon, HSRA: high-speed, hierarchical synchronous reconfigurable array, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.125-134, February 21-23, 1999, Monterey, California, United States  [doi>10.1145/296399.296442]
146
Frank Vahid, I/O and performance tradeoffs with the FunctionBus during multi-FPGA partitioning, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.27-34, February 09-11, 1997, Monterey, California, United States  [doi>10.1145/258305.258309]
 
147
Varghese, J., Butts, M., and Batcheller, J. 1993. An efficient logic emulation system. IEEE Trans. VLSI Syst. 1, 2, 171--174.
 
148
Milan Vasilko , David Cabanis, Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic Systems, Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.123, April 21-23, 1999
 
149
Jean E. Vuillemin , Patrice Bertin , Didier Roncin , Mark Shand , Hervé H. Touati , Philippe Boucard, Programmable active memories: reconfigurable systems come of age, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.4 n.1, p.56-69, March 1996  [doi>10.1109/92.486081]
 
150
Qiang Wang , D. M. Lewis, Automated field-programmable compute accelerator design using partial evaluation, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.145, April 16-18, 1997
 
151
Markus Weinhardt , Wayne Luk, Pipeline Vectorization for Reconfigurable Systems, Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.52, April 21-23, 1999
152
Steven J. E. Wilton, SMAP: heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.171-178, February 22-25, 1998, Monterey, California, United States  [doi>10.1145/275107.275137]
 
153
M. J. Wirthlin, A dynamic instruction set computer, Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines, p.99, April 19-21, 1995
154
Michael J. Wirthlin , Brad L. Hutchings, Sequencing run-time reconfigured hardware with software, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, p.122-128, February 11-13, 1996, Monterey, California, United States  [doi>10.1145/228370.228388]
155
Michael J. Wirthlin , Brad L. Hutchings, Improving functional density through run-time constant propagation, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.86-92, February 09-11, 1997, Monterey, California, United States  [doi>10.1145/258305.258316]
 
156
Wittig, R. D. and Chow, P. 1996. OneChip: An FPGA processor with reconfigurable logic. IEEE Symposium on FPGAs for Custom Computing Machines, 126--135.
157
R. Glenn Wood , Rob A. Rutenbar, FPGA routing and routability estimation via Boolean satisfiability, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.119-125, February 09-11, 1997, Monterey, California, United States  [doi>10.1145/258305.258322]
 
158
Wu, Y. L. and Marek-Sadowska, M. 1997. Routing for array-type FPGA's. IEEE Trans. CAD Integ. Circ. Syst. 16, 5, 506--518.
 
159
Xilinx, Inc. 1994. The Programmable Logic Data Book. Xilinx, Inc., San Jose, CA.
 
160
Xilinx, Inc. 1996. XC6200: Advance Product Specification. Xilinx, Inc., San Jose, CA.
 
161
Xilinx, Inc. 1997. LogiBLOX: Product Specification. Xilinx, Inc., San Jose, CA.
 
162
Xilinx, Inc. 1999. VirtexTM 2.5 V Field Programmable Gate Arrays: Advance Product Specification. Xilinx, Inc., San Jose, CA.
 
163
Xilinx, Inc. 2000. Press Release: IBM and Xilinx Team to Create New Generation of Integrated Circuits. Xilinx, Inc., San Jose, CA.
 
164
Xilinx, Inc. 2001. Virtex-II 1.5V Field Programmable Gate Arrays: Advance Product Specification. Xilinx, Inc., San Jose, CA.
 
165
Gulsun Yasar , Julie Devins , Yelena Tsyrkina , Gregg Stadtlander , Eric Millham, Growable FPGA Macro Generator, Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, p.307-316, September 23-25, 1996
 
166
Kang Yi , Chu Shik Jhon, A New FPGA Technology Mapping Approach by Cluster Merging, Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, p.366-370, September 23-25, 1996
 
167
P. Zhong , M. Martonosi , P. Ashar , S. Malik, Accelerating Boolean Satisfiability with Configurable Hardware, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.186, April 15-17, 1998

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A. K. Noor, Computing technology: frontiers and beyond, Engineering computational technology, Civil-Comp press, Edinburgh, UK, 2002
Juha-Pekka Soininen , Hannu Heusala, A design methodology for NOC-based systems, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003
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Stephen Coe , Shawki Areibi , Medhat Moussa, A hardware Memetic accelerator for VLSI circuit partitioning, Computers and Electrical Engineering, v.33 n.4, p.233-248, July, 2007
Armando Astarloa , Aitzol Zuloaga , Unai Bidarte , José Luis Martín , Jesús Lázaro , Jaime Jiménez, Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs, Journal of Systems Architecture: the EUROMICRO Journal, v.53 n.9, p.629-643, September, 2007
Sami Yehia , Olivier Temam, From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation, ACM SIGARCH Computer Architecture News, v.32 n.2, p.238, March 2004
Soheil Ghiasi , Ani Nahapetian , Hyun J. Moon , Majid Sarrafzadeh, Reconfiguration in network of embedded systems: Challenges and adaptive tracking case study, Journal of Embedded Computing, v.1 n.1, p.147-166, January 2005
K. Tatas , D. Soudris , A. Thanailakis, Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms, Journal of Embedded Computing, v.1 n.3, p.353-362, August 2005
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W. Stechele , L. Alvado Carcel , S. Herrmann , J. Lidon Simon, A Coprocessor for Accelerating Visual Information Processing, Proceedings of the conference on Design, Automation and Test in Europe, p.26-31, March 07-11, 2005
G. Chen , M. Kandemir , U. Sezer, Configuration-Sensitive Process Scheduling for FPGA-Based Computing Platforms, Proceedings of the conference on Design, automation and test in Europe, p.10486, February 16-20, 2004
A. Chattopadhyay , H. Ishebabi , X. Chen , Z. Rakosi , K. Karuri , D. Kammler , R. Leupers , G. Ascheid , H. Meyr, Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors, ACM Transactions on Embedded Computing Systems (TECS), v.7 n.4, p.1-31, July 2008
Siew-Kei Lam , Thambipillai Srikanthan, Rapid design of area-efficient custom instructions for reconfigurable embedded processing, Journal of Systems Architecture: the EUROMICRO Journal, v.55 n.1, p.1-14, January, 2009
Ivan Gonzalez , Estanislao Aguayo , Sergio Lopez-Buedo, Self-Reconfigurable Embedded Systems on Low-Cost FPGAs, IEEE Micro, v.27 n.4, p.49-57, July 2007
Dominik Goddeke , Robert Strzodka , Jamaludin Mohd-Yusof , Patrick McCormick , Hilmar Wobker , Christian Becker , Stefan Turek, Using GPUs to improve multigrid solver performance on a cluster, International Journal of Computational Science and Engineering, v.4 n.1, p.36-55, November 2008
Hamid Fadishei , Mehdi Saeedi , Morteza Saheb Zamani, A fast IP routing lookup architecture for multi-gigabit switching routers based on reconfigurable systems, Microprocessors & Microsystems, v.32 n.4, p.223-233, June, 2008
Lars Bauer , Muhammad Shafique , Jörg Henkel, Run-time instruction set selection in a transmutable embedded processor, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
Nikolaos Bellas , Sek M. Chai , Malcolm Dwyer , Dan Linzmeier, Mapping streaming architectures on reconfigurable platforms, ACM SIGARCH Computer Architecture News, v.35 n.3, June 2007
Ingo Sander , Axel Jantsch, Modelling Adaptive Systems in ForSyDe, Electronic Notes in Theoretical Computer Science (ENTCS), v.200 n.2, p.39-54, February, 2008
Safaa J. Kasbah , Issam W. Damaj , Ramzi A. Haraty, Multigrid solvers in reconfigurable hardware, Journal of Computational and Applied Mathematics, v.213 n.1, p.79-94, March, 2008
Ambrose Chu , Scott Miller , Mihai Sima, Reconfigurable solutions for very-long arithmetic with applications in cryptography, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
Andreas Raabe , Philipp A. Hartmann , Joachim K. Anlauf, ReChannel: Describing and simulating reconfigurable hardware in systemC, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.1, p.1-18, January 2008
Hashem H. Najaf-abadi , Eric Rotenberg, Architectural contesting: exposing and exploiting temperamental behavior, ACM SIGARCH Computer Architecture News, v.35 n.3, June 2007
Jesús Tabero , Julio Septién , Hortensia Mecha , Daniel Mozos, Allocation heuristics and defragmentation measures for reconfigurable systems management, Integration, the VLSI Journal, v.41 n.2, p.281-296, February, 2008
Yang Qu , Juha-Pekka Soininen , Jari Nurmi, Static scheduling techniques for dependent tasks on dynamically reconfigurable devices, Journal of Systems Architecture: the EUROMICRO Journal, v.53 n.11, p.861-876, November, 2007
Kuo-pao Yang , Theresa Beaubouef, A field programmable gate array media player for realmedia files, Journal of Computing Sciences in Colleges, v.23 n.6, June 2008
John O'Donnell, Supporting tasks with adaptive groups in data parallel programming, International Journal of Computational Science and Engineering, v.1 n.2-4, p.86-98, May 2005
Katherine Compton , Scott Hauck, Automatic design of reconfigurable domain-specific flexible cores, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.5, p.493-503, May 2008
Nastaran Baradaran , Pedro C. Diniz, A compiler approach to managing storage and memory bandwidth in configurable architectures, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.4, p.1-26, September 2008
Antonio Carlos S. Beck , Mateus B. Rutzig , Georgi Gaydadjiev , Luigi Carro, Transparent reconfigurable acceleration for heterogeneous embedded applications, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
Lars Bauer , Muhammad Shafique , Stephanie Kreutz , Jörg Henkel, Run-time system for an extensible embedded processor with dynamic instruction set, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
Rodolfo Pellizzoni , Marco Caccamo, Real-Time Management of Hardware and Software Tasks for FPGA-based Embedded Systems, IEEE Transactions on Computers, v.56 n.12, p.1666-1680, December 2007
Pao-Ann Hsiung , Chao-Sheng Lin , Chih-Feng Liao, Perfecto: A systemc-based design-space exploration framework for dynamically reconfigurable architectures, ACM Transactions on Reconfigurable Technology and Systems (TRETS), v.1 n.3, p.1-30, September 2008
Katherine Compton , Scott Hauck, Automatic Design of Area-Efficient Configurable ASIC Cores, IEEE Transactions on Computers, v.56 n.5, p.662-672, May 2007
Takashi Ajiro , Kensei Tsuchida, A Model of Computation for Bit-Level Concurrent Computing and Programming: APEC, IEICE - Transactions on Information and Systems, v.E91-D n.1, p.1-14, January 2008
Like Yan , Gang Wang , Tianzhou Chen, The input-aware dynamic adaptation of area and performance for reconfigurable accelerator, Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays, February 22-24, 2009, Monterey, California, USA
Jinhwan Kim , Jeonghun Cho , Tag Gon Kim, Temporal Partitioning to Amortize Reconfiguration Overhead for Dynamically Reconfigurable Architectures, IEICE - Transactions on Information and Systems, v.E90-D n.12, p.1977-1985, December 2007
Fabio Cancare , Marco D. Santambrogio , Donatella Sciuto, An application-centered design flow for self reconfigurable systems implementation, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan
Jason Cong , Karthik Gururaj , Guoling Han, Synthesis of reconfigurable high-performance multicore systems, Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays, February 22-24, 2009, Monterey, California, USA
Georgios P. Dimitropoulos, Agility index of automatic production systems: Reconfigurable logic and open source as agility enablers, Computers in Industry, v.60 n.4, p.248-256, May, 2009
Biswajit Sahoo , Tripti Swarnkar , Sudarsan Padhy, Implementation of parallel edit distance algorithm for protein sequences using reconfigurable accelerator, Proceedings of the International Conference on Advances in Computing, Communication and Control, January 23-24, 2009, Mumbai, India
Fernando J. Barros, Modeling and simulation of parallel adaptive divide-and-conquer algorithms, The Journal of Supercomputing, v.43 n.3, p.241-255, March 2008
Zain-ul-Abdin , Bertil Svensson, Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing, Microprocessors & Microsystems, v.33 n.3, p.161-178, May, 2009
Sotiris Xydis , George Economakos , Kiamal Pekmestzi, Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths, Integration, the VLSI Journal, v.42 n.4, p.486-503, September, 2009
Camel Tanougast , Michael Janiaut , Yves Berviller , Hassan Rabah , Serge Weber , Ahmed Bouridane, An embedded and programmable system based FPGA for real time, MPEG stream buffer analysis, IEEE Transactions on Circuits and Systems for Video Technology, v.19 n.2, p.237-249, February 2009

INDEX TERMS

Primary Classification:
  A. General Literature
  A.1 INTRODUCTORY AND SURVEY

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Logic arrays
      B.6.3 Design Aids
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays


General Terms:
Design, Performance


Keywords:
Automatic design, FPGA, field-programmable, manual design, reconfigurable architectures, reconfigurable computing, reconfigurable systems


REVIEW

"Marlin W Thomas : Reviewer"

Computer science can be seen as a tension between hardware and software, which alternate in ascendancy within the field. In the early days of computing, hardware was central to the computer science curriculum. More recently, software has been cent  more...

Collaborative Colleagues:
Katherine Compton: colleagues
Scott Hauck: colleagues

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