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Routability driven white space allocation for fixed-die standard-cell placement
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Source International Symposium on Physical Design archive
Proceedings of the 2002 international symposium on Physical design table of contents
San Diego, CA, USA
SESSION: Physical Hierarchy table of contents
Pages: 42 - 47  
Year of Publication: 2002
ISBN:1-58113-460-6
Authors
Xiaojian Yang  University of California at Los Angeles, Los Angeles, CA
Bo-Kyung Choi  University of California at Los Angeles, Los Angeles, CA
Majid Sarrafzadeh  University of California at Los Angeles, Los Angeles, CA
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 5,   Downloads (12 Months): 20,   Citation Count: 35
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ABSTRACT

The use of white space in fixed-die standard-cell placement is an effective way to improve routability. In this paper, we present a white space allocation approach that dynamically assigns white space according to the congestion distribution of the placement. In the top-down placement flow, white space is assigned to congested regions using a smooth allocating function. A post allocation optimization step is taken to further improve placement quality. Experimental results show that the proposed allocation approach, combined with a multilevel placement flow, significantly improves placement routability and layout quality.In our experiments, we compared our placement tool with two other fixed-die placers using an industrial place and route flow. Placements created by all three tools have been routed with an industrial router (Warp Route of Cadence). Compared with a leading-edge industrial tool, our placer produces placements with similar or better routability and on average 8.8% shorter routed wirelength. Furthermore, our tool produces placement that runs faster through the Warp Route compared with the industrial tool. Compared with a state-of-the-art academic placement tool (Capo/MetaPlacer), our placer shows ability to produce more routable placements: for 15 out of all 16 benchmarks our placer's outputs are routable while Capo/MetaPlacer only creates 4 routable placements.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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J. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich. "GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization". IEEE Transactions on Computer Aided Design, 10(3):365--365, 1991.
 
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S. Mayrhofer and U. Lauther. "Congestion-Driven Placement Using a New Multi-partitioning Heuristic". In International Conference on Computer-Aided Design, pages 332--335. IEEE, 1990.
 
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M. Wang, X. Yang, and M. Sarrafzadeh. "Congestion Minimization During Placement". IEEE Transactions on Computer Aided Design, 19(10):1140--1148, 2000.
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NuCAD. "IBM-PLACE benchmark". http://www.ece.nwu.edu/nucad/ibm-place.html.

CITED BY  35

Collaborative Colleagues:
Xiaojian Yang: colleagues
Bo-Kyung Choi: colleagues
Majid Sarrafzadeh: colleagues