FPGA interconnect planning

ABSTRACT

We present an FPGA interconnect planning methodology based on the empirical measure known as Rent's Rule[8]. We show that allocation of wire segment lengths during the FPGA architecture planning phase can be improved by taking into account intercon¿nect complexities of the target circuits. We utilize previous work on netlist circuit fanout distribution[12] to estimate the FPGA seg¿mentation and employ a timing-driven placement and routing approach to get a minimized area-delay product. Our results indi¿cate that for logic clusters of various complexities, embedded in hierarchical FPGAs, our interconnect planning technique can improve circuit performance by an average of 10% and the area-delay product by an average of 29% over typical commercial FPGAs.

REFERENCES

• 1: Vaughn Betz , Jonathan Rose, VPR: A new packing, placement and routing tool for FPGA research, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.213-222, September 01-03, 1997
• 2: Vaughn Betz , Jonathan Rose , Alexander Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, Norwell, MA, 1999
• 3: V. Betz and J. Rose, "Circuit Design, Transistor Sizing and Wire Layout of FPGA Interconnect,'' IEEE Custom Integrated Circuits Conference, San Diego, CA, May 1999, pp. 171 - 174.
• 4: Vaughn Betz , Jonathan Rose, FPGA routing architecture: segmentation and buffering to optimize speed and density, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.59-68, February 21-23, 1999, Monterey, California, United States [doi>10.1145/296399.296428]
• 5: J.A. Davis, V.K. De, and J.D. Meindl, "A Stochastic Wire Length Distribution for Gigascale Integration (GSI) Part I: Derivation and Validation", IEEE Transactions on Electron Devices, vol. 45, no. 3, pp. 580-589, March 1998.
• 6: J.A. Davis, V.K De, and J.D. Meindl, "A Stochastic Wire Length Distribution for Gigascale Integration (GSI) Part II: Applications to Clock Frequency, Power Dissipation, and Chip Size Estimation", IEEE Transactions on Electron Devices, vol. 45, no. 3, pp. 590-597, March 1998.
• 7: W.E. Donath, "Placement and Average Interconnect requirements of Computer logic", IEEE Trans. Circuits and Systems, CAS-26:272-277, 1979.
• 8: B.S. Landman, R.L. Russo, "On a pin versus block relationship for partitions of logic graphs", IEEE Trans. on Computers, C-20: 1469-1479, 1974.
• 9: Amit Singh , Arindam Mukherjee , Malgorzata Marek-Sadowska, Interconnect pipelining in a throughput-intensive FPGA architecture, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.153-160, February 2001, Monterey, California, United States [doi>10.1145/360276.360323]
• 10: Amit Singh , Malgorzata Marek-Sadowska, Efficient circuit clustering for area and power reduction in FPGAs, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA [doi>10.1145/503048.503058]
• 11: H. Van Marck, D. Stroobandt, J. Van Campenhout, "Towards an extension of Rent's rule for describing local variations in interconnect complexity" Proc. 4th Intl. Symposium for Young Computer Scientists, pp.136-141, 1995.
• 12: P. Zarkesh-Ha, J.A. Davis, W. Loh, J.D. Meindl, "Stochastic interconnect network fan-out distribution using Rent's rule. Proceedings of the IEEE 1998 International Interconnect Technology Conference, San Francisco, CA, USA, 1-3 June 1998.) New York, NY, USA: IEEE, 1998. p.184-6.
• 13: Payman Zarkesh-Ha , Jeffrey A. Davis , James D. Meindl, Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.8 n.6, p.649-659, Dec. 2000 [doi>10.1109/92.902259]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

General Terms:
Design, Experimentation, Performance