| A new look at hardware maze routing |
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Great Lakes Symposium on VLSI
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Proceedings of the 12th ACM Great Lakes symposium on VLSI
table of contents
New York, New York, USA
SESSION: Design Automation
table of contents
Pages: 142 - 147
Year of Publication: 2002
ISBN:1-58113-462-2
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Downloads (6 Weeks): 1, Downloads (12 Months): 19, Citation Count: 0
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ABSTRACT
This paper describes a new design for a hardware accelerator to support grid-based Maze Routing. Based on the direct mapped approach of Breuer and Shamsa [3], this work refines their design to substantially reduce the hardware requirements of each processing element while at the same time adding support for mulitilayer routing and fast iterative routing. An RTL implementation has been developed for this design in VHDL, and initial results show promise for its realization using ASIC, custom, or FPGA technology.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Lee, C. Y. "An Algorithm for Path Connections and its Applications," IRE Transactions on Electronic Computers vol. EC-10, no. 2, pp. 346-365, 1961.
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Akers, S. "A Modification of Lee's Path Connection Algorithm," IEEE Trans. Electronic Computers vol. EC-16, no. 2, pp. 97-98, 1967.
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Breuer, M., and Shamsa, K. "A Hardware Router," Journal of Digital Systems, vol. IV, no. 4, pp. 393-408, 1981.
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Suzuki, K., et. al., "A Hardware Maze Router with Application to Interactive Rip-Up and Reroute," IEEE Trans. CAD, vol. CAD-5, no. 4, pp. 466-476, 1986.
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Watanabe, T., et. al., "A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor", IEEE Trans. CAD, vol. CAD-6, no. 2, 1987.
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Ventkateswaran, R., and Mazumder, P., "Coprocessor Design for Multilayer Surface-Mounted PCB Routing,", IEEE Trans. VLSI Systems, vol. 1, no. 1, 1993.
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Xilinx, Inc., Xilinx Databook, 2001. Available online at http://www.xilinx.com.
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