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Cryptographic rights management of FPGA intellectual property cores
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Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays table of contents
Monterey, California, USA
Session: Cellular and Cryptographic Applications table of contents
Pages: 113 - 118  
Year of Publication: 2002
ISBN:1-58113-452-5
Author
Tom Kean  Algotronix Ltd., Edinburgh, United Kingdom
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 7,   Downloads (12 Months): 31,   Citation Count: 3
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ABSTRACT

As the capacity of FPGA's increases to millions of equivalent gates the use of Intellectual Property (IP) cores becomes increasingly important to control design complexity. FPGA's are becoming platforms for integrating a system solution from components supplied by independent vendors in the same way as printed circuit boards provided a platform for earlier generations of designers. However, the current commercial model for IP cores involves large up-front license fees reminiscent of ASIC NRE charges. In order to match the IP core business model to the low to medium volume applications addressed by FPGA customers it is important to develop cryptographic techniques which allow IP core vendors to sell their product on a pay-per-use basis rather than through up-front license fees.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Dipert, B., "Cunning Circuits Confound Crooks," EDN Magazine, October 12, 2000.
 
2
Actel Corporation, "Protecting your Intellectual Property from the Pirates", presentation at DesignCon '98. Available from www.actel.com.
 
3
Xilinx Inc., "Using Bitstream Encryption", in Chapter 2 of the Virtex II Platform FPGA Handbook available from www.xilinx.com.
 
4
Austin, K., US Patent 5,388,157 "Data Security Arrangements for Semiconductor Programmable Devices"
 
5
Algotronix Ltd., "Method and Apparatus for Secure Configuration of a Field Programmable Gate Array", PCT Patent Application PCT/GB00/04988.
 
6
Algotronix Ltd., "Method of using a Mask Programmed Key to Securely Configure a Field Programmable Gate Array", European Patent Application EP01124330A2.
 
7
 
8
Schneier, B., "Applied Cryptography", 2nd edition, Wiley, 1996.
 
9
Altera Inc., "Evaluating AMPP and MegaCore Functions", AN-125, April 2000, available from www.altera.com .
 
10
Algotronix Ltd., "Method of Protecting Intellectual Property Cores on Field Programmable Gate Array", unpublished pending patent application.