Circuit design of routing switches

ABSTRACT

This paper examines circuit design of buffered routing switches in symmetrical, island-style FPGAs. The effects of switch size, tile length, level-restoring, and slow input slew rates are examined. Two new fanin-based switch designs are used to eliminate nearly all of the increase in delay that arises from fanout with a previous switch design. Alternating between buffers and pass transistors is shown to improve connection delay without fanout by 25%. To take advantage of this, we propose schemes to replace some buffers with pass transistors to simultaneously reduce area and delay. Routing a suite of MCNC benchmark circuits shows that 14% in area-delay, or 7% in delay can be saved using the new switch schemes. Alternatively, approximately 13% in area can be saved with no degradation to delay.

REFERENCES

• 1: Vaughn Betz , Jonathan Rose , Alexander Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, Norwell, MA, 1999
• 2: I. Dobbelaere, M. Horowitz, and A. El Gamal, "Regenerative feedback repeaters for programmable interconnections," IEEE Journal of Solid-State Circuits, vol. 30, no. 11, 1995.
• 3: Paul Chow , Soon Ong Seo , Jonathan Rose , Kevin Chung , Gerard Páez-Monzón , Immanuel Rahardja, The design of a SRAM-based field-programmable gate array—part II: circuit design and layout, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.3, p.321-330, Sept. 1999 [doi>10.1109/92.784093]
• 4: M. Khellah, S. Brown, and Z. Vranesic, "Modelling routing delays in SRAM-based FPGAs," in Canadian Conference on VLSI, pp. 6B.13-18, November 1993.
• 5: Emil S. Ochotta , Patrick J. Crotty , Charles R. Erickson , Chih-Tsung Huang , Rajeev Jayaraman , Richard C. Li , Joseph D. Linoff , Luan Ngo , Hy V. Nguyen , Kerry M. Pierce , Douglas P. Wieland , Jennifer Zhuang , Scott S. Nance, A novel predictable segmented FPGA routing architecture, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.3-11, February 22-25, 1998, Monterey, California, United States [doi>10.1145/275107.275111]
• 6: Steve Trimberger , Khue Duong , Bob Conn, Architecture issues and solutions for a high-capacity FPGA, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.3-9, February 09-11, 1997, Monterey, California, United States [doi>10.1145/258305.258306]
• 7: Xilinx, San Jose, CA, Online Data Books, 2001.
• 8: Mike Sheng , Jonathan Rose, Mixing buffers and pass transistors in FPGA routing architectures, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.75-84, February 2001, Monterey, California, United States [doi>10.1145/360276.360302]
• 9: Vaughn Betz , Jonathan Rose, VPR: A new packing, placement and routing tool for FPGA research, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.213-222, September 01-03, 1997
• 10: Guy Lemieux , David Lewis, Using sparse crossbars within LUT, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.59-68, February 2001, Monterey, California, United States [doi>10.1145/360276.360299]
• 11: V. Betz and J. Rose, "Circuit design, transistor sizing, and wire layout of FPGA interconnect," in Custom Integraged Circuits Conference, pp. 171-174, May 1999.
• 12: Elias Ahmed , Jonathan Rose, The effect of LUT and cluster size on deep-submicron FPGA performance and density, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.3-12, February 10-11, 2000, Monterey, California, United States [doi>10.1145/329166.329171]
• 13: Jan M. Rabaey, Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
• 14: K. Martin, Digital Integrated Circuit Design. New York, NY: Oxford University Press, 2000.
• 15: Alexander Marquardt , Vaughn Betz , Jonathan Rose, Speed and area tradeoffs in cluster-based FPGA architectures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.8 n.1, p.84-93, Feb. 2000 [doi>10.1109/92.820764]