A software development tool chain for a reconfigurable processor

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A software development tool chain for a reconfigurable processor

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International Conference on Compilers, Architecture and Synthesis for Embedded Systems archive
Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems table of contents

Atlanta, Georgia, USA

Session: Synthesis and Design Tools table of contents

Pages: 93 - 98

Year of Publication: 2001

ISBN:1-58113-399-5

Authors

Alberto La Rosa	Dipartimento di Elettronica, Politecnico di Torino, Italy
Luciano Lavagno	Dipartimento di Elettronica, Politecnico di Torino, Italy
Claudio Passerone	Dipartimento di Elettronica, Politecnico di Torino, Italy

Sponsors

NS : National Semicondutor
IBM : IBM
ARM : ARM
cadence : cadence
ACM: Association for Computing Machinery
STARCORE : STARCORE

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 9, Downloads (12 Months): 49, Citation Count: 6

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	3	Timothy J. Callahan , John R. Hauser , John Wawrzynek, The Garp Architecture and C Compiler, Computer, v.33 n.4, p.62-69, April 2000 [doi>10.1109/2.839323]
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CITED BY 6

	Massimo Baleani , Frank Gennari , Yunjian Jiang , Yatish Patel , Robert K. Brayton , Alberto Sangiovanni-Vincentelli, HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform, Proceedings of the tenth international symposium on Hardware/software codesign, May 06-08, 2002, Estes Park, Colorado
	Andrea Lodi , Mario Toma , Fabio Campi, A pipelined configurable gate array for embedded processors, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	A. Chattopadhyay , W. Ahmed , K. Karuri , D. Kammler , R. Leupers , G. Ascheid , H. Meyr, Design space exploration of partially re-configurable embedded processors, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Alberto La Rosa , Claudio Passerone , Francesco Gregoretti , Luciano Lavagno, Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform, Proceedings of the conference on Design, automation and test in Europe, p.21218, February 16-20, 2004
	A. Chattopadhyay , H. Ishebabi , X. Chen , Z. Rakosi , K. Karuri , D. Kammler , R. Leupers , G. Ascheid , H. Meyr, Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors, ACM Transactions on Embedded Computing Systems (TECS), v.7 n.4, p.1-31, July 2008
	Kingshuk Karuri , Anupam Chattopadhyay , Xiaolin Chen , David Kammler , Ling Hao , Rainer Leupers , Heinrich Meyr , Gerd Ascheid, A design flow for architecture exploration and implementation of partially reconfigurable processors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.10, p.1281-1294, October 2008