A new method for compiling schizophrenic synchronous programs

ABSTRACT

Synchronous programming languages have proved to be advantageous for designing software and hardware for embedded systems. Despite their clear semantics, their compilation is remarkably difficult: In particular, one has to take care of potential schizophrenia problems. Although these problems are correctly translated with existing compilers, there is still a need for clean algorithms. In this paper, we present the first solution to eliminate schizophrenia problems by program transformations. These transformations are used for compilation, but also for increasing the readability of programs.

REFERENCES

• 1: Gérard Berry, The foundations of Esterel, Proof, language, and interaction: essays in honour of Robin Milner, MIT Press, Cambridge, MA, 2000
• 2: G. Berry. The constructive semantics of pure Esterel, July 1999.
• 3: G. Berry. The Esterel v5_91 language primer. http://www.esterel.org, June 2000.
• 4: F. Boussinot. SugarCubes implementation of causality. Research Report 3487, INRIA, Sophia Antipolis Cedex, France, September 1998.
• 5: J. Brzozowski and C.-J. Seger. Asynchronous Circuits. Springer Verlag, 1995.
• 6: Cadence Design Systems,Inc. Website, 2000. http://www.cadence.com.
• 7: Esterel Web. Website, 2000. http://www.esterel.org.
• 8: A. Girault and G. Berry. Circuit generation and verification of Esterel programs. Research report 3582, INRIA, December 1998.
• 9: M. J. C. Gordon , T. F. Melham, Introduction to HOL: a theorem proving environment for higher order logic, Cambridge University Press, New York, NY, 1993
• 10: N. Halbwachs and F. Maraninchi. On the symbolic analysis of combinational loops in circuits and synchronous programs. In Euromicro Conference, Como, Italy, September 1995.
• 11: Jester Home Page. Website, 2000. http://www.parades.rm.cnr.it/projects/jester/jester.html.
• 12: Luciano Lavagno , Ellen Sentovich, ECL: a specification environment for system-level design, Proceedings of the 36th ACM/IEEE conference on Design automation, p.511-516, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309989]
• 13: S. Malik. Analysis of cycle combinational circuits. IEEE Transactions on Computer Aided Design, 13(7):950-956, July 1994.
• 14: POLIS Homepage, 2000. http://www-cad.eecs.berkeley.edu/
• 15: Klaus Schneider, A Verified Hardware Synthesis of Esterel Programs, Proceedings of the IFIP WG10.3/WG10.4/WG10.5 International Workshop on Distributed and Parallel Embedded Systems: Architecture and Design of Distributed Embedded Systems, p.205-214, October 18-19, 2000
• 16: K. Schneider, Embedding Imperative Synchronous Languages in Interactive Theorem Provers, Proceedings of the Second International Conference on Application of Concurrency to System Design, p.143, June 25-29, 2001
• 17: Thomas R. Shiple , Gerard Berry , Herve Touati, Constructive Analysis of Cyclic Circuits, Proceedings of the 1996 European conference on Design and Test, p.328, March 11-14, 1996

INDEX TERMS

Primary Classification:
  I. Computing Methodologies
  I.2 ARTIFICIAL INTELLIGENCE
      I.2.2 Automatic Programming
          Subjects: Program transformation

Additional Classification:
  B. Hardware
  B.1 CONTROL STRUCTURES AND MICROPROGRAMMING
      B.1.4 Microprogram Design Aids
          Subjects: Languages and compilers

  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

General Terms:
Algorithms, Design, Performance

Keywords:
code generation, reactive systems, synchronous languages