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Heterogeneous memory management for embedded systems
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Source International Conference on Compilers, Architecture and Synthesis for Embedded Systems archive
Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems table of contents
Atlanta, Georgia, USA
Session: Caches and Memory Systems table of contents
Pages: 34 - 43  
Year of Publication: 2001
ISBN:1-58113-399-5
Authors
Oren Avissar  University of Maryland, College Park, MD
Rajeev Barua  University of Maryland, College Park, MD
Dave Stewart  Embedded Research Solutions, LLC, Columbia, MD
Sponsors
NS : National Semicondutor
IBM : IBM
ARM : ARM
cadence : cadence
ACM: Association for Computing Machinery
STARCORE : STARCORE
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 20,   Downloads (12 Months): 74,   Citation Count: 15
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ABSTRACT

This paper presents a technique for the efficient compiler management of software-exposed heterogeneous memory. In many lower-end embedded chips, often used in micro-controllers and DSP processors, heterogeneous memory units such as scratch-pad SRAM, internal DRAM, external DRAM and ROM are visible directly to the software, without automatic management by a hardware caching mechanism. Instead the memory units are mapped to different portions of the address space. Caches are avoided because of their cost and power consumption, and because they make it difficult to guarantee real-time performance. For this important class of embedded chips, the allocation of data to different memory units to maximize performance is the responsibility of the software.Current practice typically leaves it to the programmer to partition the data among the different memory units. We present a compiler strategy that automatically partitions the data among the memory units. We show that this strategy is optimal among all static partitions for global and stack data, and a good heuristic for heap data. For global and stack data, the scheme is provably equal to or better than any other compiler scheme or set of programmer annotations. Preliminary results show the benefits of optimal allocation: with just 20% of the data in SRAM, the formulation is able to decrease the runtime by 39% on average for our benchmarks vs. allocating all data to slow memory, without any programmer involvement. For some programs, less than 5% of data in SRAM achieves a similar speedup.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY  15

Collaborative Colleagues:
Oren Avissar: colleagues
Rajeev Barua: colleagues
Dave Stewart: colleagues