| Heterogeneous memory management for embedded systems |
| Full text |
Pdf
(241 KB)
|
| Source
|
International Conference on Compilers, Architecture and Synthesis for Embedded Systems
archive
Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
table of contents
Atlanta, Georgia, USA
Session: Caches and Memory Systems
table of contents
Pages: 34 - 43
Year of Publication: 2001
ISBN:1-58113-399-5
|
|
Authors
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 20, Downloads (12 Months): 74, Citation Count: 15
|
|
|
ABSTRACT
This paper presents a technique for the efficient compiler management of software-exposed heterogeneous memory. In many lower-end embedded chips, often used in micro-controllers and DSP processors, heterogeneous memory units such as scratch-pad SRAM, internal DRAM, external DRAM and ROM are visible directly to the software, without automatic management by a hardware caching mechanism. Instead the memory units are mapped to different portions of the address space. Caches are avoided because of their cost and power consumption, and because they make it difficult to guarantee real-time performance. For this important class of embedded chips, the allocation of data to different memory units to maximize performance is the responsibility of the software.Current practice typically leaves it to the programmer to partition the data among the different memory units. We present a compiler strategy that automatically partitions the data among the memory units. We show that this strategy is optimal among all static partitions for global and stack data, and a good heuristic for heap data. For global and stack data, the scheme is provably equal to or better than any other compiler scheme or set of programmer annotations. Preliminary results show the benefits of optimal allocation: with just 20% of the data in SRAM, the formulation is able to decrease the runtime by 39% on average for our benchmarks vs. allocating all data to slow memory, without any programmer involvement. For some programs, less than 5% of data in SRAM achieves a similar speedup.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
 |
1
|
|
| |
2
|
|
| |
3
|
S.S.Bhattacharyya,R.Leupers,and P.Marwedel. Software Synthesis and Code Generation for Signal Processing Systems.IEEE Transactions on Circuits and Systems ,47(9),September 2000.
|
| |
4
|
T.T.Consortium.The Trimaran benchmark suite. Available at http://www.trimaran.org/,1999.
|
 |
5
|
|
| |
6
|
|
| |
7
|
|
| |
8
|
Matlab 6.1 .The Math Works,Inc.,2001. http://www.mathworks.com/products/matlab/.
|
| |
9
|
|
| |
10
|
CPU12 Reference Manual .Motorola Corporation, 2000.http://e-www.motorola.com/brdata/PDFDB/- MICROCONTROLLERS/16 BIT/- 68HC12 FAMI LY/REF MAT/CPU12RM.pdf.
|
| |
11
|
M-CORE -MMC2001 Reference Manual .Motorola Corporation,1998.http://www.motorola.com/SPS/- MCORE/info documentation.htm.
|
| |
12
|
New York City,O .ce of Budget and Management. Website on frequently asked questions on linear programming . http://www.eden.rutgers.edu/~pil/FAQ.html,New York,NY,1999.
|
 |
13
|
|
| |
14
|
P.Paulin,C.Liem,M.Cornero,F.Nacabal,and G.Goossens.Embedded Software in Real-Time Signal Processing Systems:Application and Architecture Trends.Invited paper,Proceedings of the IEEE ,85(3), March 1997.
|
| |
15
|
P.Rutter,J.Orost,and D.Gloistein.BTOA:Binary to printable ASCII converter source code.Available at http://www.bookcase.com/library/software/- msdos.devel.lang.c.html .
|
| |
16
|
J.Sjodin,B.Froderberg,and T.Lindgren.Allocation of Global Data Objects in On-Chip RAM.Compiler and Architecture Support for Embedded Computing Systems ,December 1998.
|
| |
17
|
TMS370Cx7x 8-bit microcontroller .Texas Instruments,Revised Feb.1997.http://wwws.ti.com/sc/psheets/spns034c/spns034c.pdf.
|
CITED BY 15
|
|
|
|
|
Nghi Nguyen , Angel Dominguez , Rajeev Barua, Memory allocation for embedded systems with a compile-time-unknown scratch-pad size, Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, September 24-27, 2005, San Francisco, California, USA
|
|
|
|
|
|
|
|
|
|
|
|
Poletti Francesco , Paul Marchal , David Atienza , Luca Benini , Francky Catthoor , Jose M. Mendias, An integrated hardware/software approach for run-time scratchpad management, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
|
|
|
|
|
|
|
|
|
|
|
|
Nghi Nguyen , Angel Dominguez , Rajeev Barua, Scratch-pad memory allocation without compiler support for java applications, Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, September 30-October 03, 2007, Salzburg, Austria
|
|
|
|
|
|
|
|
|
Angel Dominguez , Nghi Nguyen , Rajeev K. Barua, Recursive function data allocation to scratch-pad memory, Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, September 30-October 03, 2007, Salzburg, Austria
|
|
|
|
|
|
|
|