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Storage allocation for embedded processors
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Source International Conference on Compilers, Architecture and Synthesis for Embedded Systems archive
Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems table of contents
Atlanta, Georgia, USA
Session: Caches and Memory Systems table of contents
Pages: 15 - 23  
Year of Publication: 2001
ISBN:1-58113-399-5
Authors
Jan Sjödin  Uppsala University, Uppsala, Sweden
Carl von Platen  IAR Systems, Malmö, Sweden
Sponsors
NS : National Semicondutor
IBM : IBM
ARM : ARM
cadence : cadence
ACM: Association for Computing Machinery
STARCORE : STARCORE
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 2,   Downloads (12 Months): 36,   Citation Count: 16
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ABSTRACT

In an embedded system, it is common to have several memory areas with different properties, such as access time and size. An access to a specific memory area is usually restricted to certain native pointer types. Different pointer types vary in size and cost. For example, it is typically cheaper to use an 8-bit pointer than a 16-bit pointer. The problem is to allocate data and select pointer types in the most effective way. Frequently accessed variables should be allocated in fast memory, and frequently used pointers and pointer expressions should be assigned cheap pointer types. Common practice is to perform this task manually.We present a model for storage allocation that is capable of describing architectures with irregular memory organization and with several native pointer types. This model is used in an integer linear programming (ILP) formulation of the problem. An ILP solver is applied to get an optimal solution under the model. We describe allocation of global variables and local variables with static storage duration.A whole program optimizing C compiler prototype was used to implement the allocator. Experiments were performed on the Atmel AVR 8-bit microcontroller [2] using small to medium sized C programs. The results varied with the benchmarks, with up to 8% improvement in execution speed and 10% reduction in code size.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Atmel Corporation.The AVR Instruction Set http://www.atmel.com/atmel/acrobat/doc0865.pdf
 
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J.Sjodin,B.Fr~derberg,and T.Lindgren -.Allocation of global data object in on-chip ram.Presented at the CASES '98 workshop,http://www.capsl.udel.edu/ conferences/cases99/cases98/paper04.ps
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CITED BY  17

Collaborative Colleagues:
Jan Sjödin: colleagues
Carl von Platen: colleagues