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Building a robust software-based router using network processors
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Source ACM Symposium on Operating Systems Principles archive
Proceedings of the eighteenth ACM symposium on Operating systems principles table of contents
Banff, Alberta, Canada
SESSION: Event-driven architectures table of contents
Pages: 216 - 229  
Year of Publication: 2001
ISBN:1-58113-389-8
Also published in ...
Authors
Tammo Spalink  Princeton University, Princeton, NJ
Scott Karlin  Princeton University, Princeton, NJ
Larry Peterson  Princeton University, Princeton, NJ
Yitzchak Gottlieb  Princeton University, Princeton, NJ
Sponsor
SIGOPS: ACM Special Interest Group on Operating Systems
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 8,   Downloads (12 Months): 83,   Citation Count: 36
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ABSTRACT

Recent efforts to add new services to the Internet have increased interest in software-based routers that are easy to extend and evolve. This paper describes our experiences using emerging network processors---in particular, the Intel IXP1200---to implement a router. We show it is possible to combine an IXP1200 development board and a PC to build an inexpensive router that forwards minimum-sized packets at a rate of 3.47Mpps. This is nearly an order of magnitude faster than existing pure PC-based routers, and sufficient to support 1.77Gbps of aggregate link bandwidth. At lesser aggregate line speeds, our design also allows the excess resources available on the IXP1200 to be used robustly for extra packet processing. For example, with 8 × 100Mbps links, 240 register operations and 96 bytes of state storage are available for each 64-byte packet. Using a hierarchical architecture we can guarantee line-speed forwarding rates for simple packets with the IXP1200, and still have extra capacity to process exceptional packets with the Pentium. Up to 310Kpps of the traffic can be routed through the Pentium to receive 1510 cycles of extra per-packet processing.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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A. T. Campbell, S. Chou, M. E. Konnavis, and V. D. Stachtos. Implementing Routelets: Virtual Router Support for the IXP1200 Network Processor. In/XA Univeristy Program Workshop, Portland, Oregon, June 2001.
 
3
M. Dasen, G. Fankhauser, and B. Plattner. An Error Tolerant, Scalable Video Stream Encoding and Compression for Mobile Computing. In Proceedings of ACTS Mobile Summit 96, pages 762-771, November 1996.
 
4
 
5
6
 
7
M. E. Fiuczynski, R. E Martin, T. Owa, and B. N. Bershad. On Using Intelligent Network Interface Cards to support Multimedia Applications. In Proceedings of the 8th International Workshop on Network and Operating System Support for Digital Audio and Video, pages 95-98, July 1998.
 
8
IBM Microelectronics Division. IBM PowerNP NP4GS3 Network Processor Solutions Product Overview, April 2001.
 
9
IEEE. Standard 802.3, October 2000.
 
10
Intel Corporation. IXP12OONetworkProcessorDatasheet, September 2000.
 
11
Intelligent I/O (I20) Special Interest Group. Intelligent I/O (I20) Architecture Specification, Version 2.0, March 1999.
 
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S. Karlin and L. Peterson. VERA: An Extensible Router Architecture. In Proceedings of the 4th International Conference on Open Architectures and Network Programming (OPENARCH), pages 3-14, April 2001.
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M. E. Kounavis, A. T. Campell, S. Chou, E Modoux, J. Vicente, and H. Zhuang. The Genesis Kernel: A Programming System for Spawning Network Architectures. IEEE Journal on Selected Areas in Communications, 19(3):511-526, March 2001.
15
16
17
 
18
19
 
20
 
21
22
 
23
D. E. Taylor, J. S. Turner, and J. W. Lockwood. Dynamic Hardware Plugins (DHP): Exploiting Reconfigurable Hardware for High-Performance Programmable Routers. In Proceedings of the 4th International Conference on Open Architectures and Network Programming ( OPENARCH), pages 25-34, April 2001.
 
24
C. B. S. Traw and J. M. Smith. Hardware/Software Organization of a High-Performance ATM Host Interface. 1EEE Journal on Selected Areas in Communications (Special Issue on High Speed Computer/Network Interfaces), 11(2):240-253, 1993.
 
25
Vitesse Semiconductor Corporation. IQ2000 Network Processor Product Brief, 2000.
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CITED BY  37

Collaborative Colleagues:
Tammo Spalink: colleagues
Scott Karlin: colleagues
Larry Peterson: colleagues
Yitzchak Gottlieb: colleagues