| Experiments with the peripheral virtual component interface |
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International Symposium on Systems Synthesis
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Proceedings of the 13th international symposium on System synthesis
table of contents
Madrid, Spain
SESSION: System design methodologies and experiences
table of contents
Pages: 221 - 224
Year of Publication: 2000
ISBN:1080-1082
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Authors
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Roman L. Lysecky
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Department of Computer Science and Engineering, University of California, Riverside, rlysecky@cs.ucr.edu, www.cs.ucr.edu/~dalton
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Frank Vahid
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Department of Computer Science and Engineering, University of California, Riverside; also with the Center for Embedded Computer Systems, UC Irvine vahid@cs.ucr.edu, www.cs.ucr.edu/~dalton
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Tony D. Givargis
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Department of Computer Science and Engineering, University of California, Riverside, givargis@cs.ucr.edu, www.cs.ucr.edu/~dalton
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IEEE Computer Society
Washington, DC, USA
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Downloads (6 Weeks): 0, Downloads (12 Months): 6, Citation Count: 2
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ABSTRACT
The Peripheral Virtual Component Interface, or PVCI, is a standard intended to simplify the interfacing of peripheral cores to on-chip buses in a system-on-a-chip, by standardizing the interface between a core's internals and its bus wrapper. We provide results of experiments intended to determine the power, performance, and size overhead associated with using a PVCI bus wrapper versus using a non-PVCI bus wrapper, and versus using no bus wrapper at all. The results demonstrate that using a bus wrapper may result in only small performance, power and size overhead versus using no wrapper, though even that performance overhead can be reduced or eliminated using pre-fetching. The results also demonstrate that using a PVCI bus wrapper yields no significant additional power, performance or size overhead compared with a non-PVCI bus wrapper.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Semiconductor Industry Association Roadmap 1997, http://notes.sematech.org/ntrs/PublNTRS.nsf.
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Roman L. Lysecky , Frank Vahid , Tony D. Givargis, Techniques for reducing read latency of core bus wrappers, Proceedings of the conference on Design, automation and test in Europe, p.84-91, March 27-30, 2000, Paris, France
[doi> 10.1145/343647.343710]
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Steven Vercauteren , Bill Lin , Hugo De Man, Constructing application-specific heterogeneous embedded architectures from custom HW/SW applications, Proceedings of the 33rd annual conference on Design automation, p.521-526, June 03-07, 1996, Las Vegas, Nevada, United States
[doi> 10.1145/240518.240617]
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CITED BY 2
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Damien Lyonnard , Sungjoo Yoo , Amer Baghdadi , Ahmed A. Jerraya, Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip, Proceedings of the 38th conference on Design automation, p.518-523, June 2001, Las Vegas, Nevada, United States
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