Object oriented hardware synthesis and verification

ABSTRACT

The synthesis of hardware from object oriented specifications is presented. Our approach utilizes the e language that has been proven to be highly efficient for the verification of hardware. The e language is similar to Java and provides additional constructs for specification and verification of hardware. We describe an automated design flow for the synthesis of object oriented descriptions that tightly integrates simulation based verification. The usability of our approach is demonstrated by real-world examples.

REFERENCES

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INDEX TERMS

Primary Classification:
  D. Software
  D.2 SOFTWARE ENGINEERING
      D.2.1 Requirements/Specifications
          Subjects: Methodologies (e.g., object-oriented, structured)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Algorithms implemented in hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: System architectures
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Reliability, availability, and serviceability

General Terms:
Design, Performance, Reliability, Verification

Keywords:
high-level synthesis, object oriented hardware modeling, verification