Data cache energy minimizations through programmable tag size matching to the applications

ABSTRACT

An application-specific customization methodology for minimizing the energy dissipation in the data cache of embedded processors is presented in this paper. The data cache subsystem is one of the most power consuming microarchitectural parts of embedded processors. We target in this work particularly the data cache tag operations and show how an exceedingly small number of tag bits, if any, are needed to compute the miss/hit behavior for the vast majority of load/store instructions executed within application loops. The energy needed to perform the tag reads and comparisons can be thus dramatically reduced. We follow up this conceptual enhancement with a presentation of an efficient, reprogrammable implementation that utilizes application-specific information to apply the suggested energy minimization approach. The conducted experimental results confirm the expected significant decrease of energy dissipation for a set of important numerical kernels.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Cache memories

Additional Classification:
  F. Theory of Computation
  F.2 ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY
      F.2.2 Nonnumerical Algorithms and Problems
          Subjects: Sequencing and scheduling
  F.4 MATHEMATICAL LOGIC AND FORMAL LANGUAGES
      F.4.1 Mathematical Logic
          Subjects: Computational logic

General Terms:
Design, Experimentation, Performance