RTL semantics and methodology

ABSTRACT

In the past, the EDA industry and designers have struggled with the issues of having multiple languages in use for describing, implementing and verifying their designs, such as Verilog and VHDL. This has led to gross inefficiencies in the industry with tool vendors needing to support multiple languages, which are often dissimilar, and in some cases contradictory, and with users having to deal with incompatible library issues. With the industry embarking on the search for new system level languages we already have several languages based on C or C++ that are emerging and the distinct possibility is arising that we will again be faced with language "wars". In order to prevent this we need to ensure a minimum level of compatibility between them so that it can guaranteed that information could be moved from one language to another without loss of information. It is for this reason that an Accellera working group was formed with the intention of creating a standardized set of semantics that can be shared between all of the language organization. This paper will take a look at the progress made by the group and its results to date.

REFERENCES

• 1: Accellera proposed standard http://www.eda.org/alc-cwg
• 2: Gajski, Dutt, Wu, Lin; "High-Level Synthesis," Kluwer Academic Publishers,1992
• 3: John F. Wakerly, Digital design: principles and practices (2nd ed.), Prentice-Hall, Inc., Upper Saddle River, NJ, 1994
• 4: Randy H. Katz, Contemporary logic design, Benjamin-Cummings Publishing Co., Inc., Redwood City, CA, 1993
• 5: Daniel D. Gajski, Principles of digital design, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996

INDEX TERMS

Primary Classification:
  D. Software
  D.3 PROGRAMMING LANGUAGES
      D.3.3 Language Constructs and Features

General Terms:
Languages, Standardization, Theory

Keywords:
FSMD, RTL processor, RTL semantics, accellera