Design and simulation of a pipelined decompression architecture for embedded systems

ABSTRACT

In the past, systems utilizing code compression have been shown to be advantageous over traditional systems especially in terms of smaller memory need. However, in order to take full advantage of other design criteria like increasing performance and/or minimizing power consumption, the decompression should take place as close as possible to the CPU. We have designed such a decompression unit that, in spite of the higher bandwidth constraints close to the CPU, does improve performance and minimize power consumption of a whole embedded system. By means of extensive simulations we have designed and eventually sized the various parameters of the decompression engine #pipelines, #pipeline stages, input/output buffer sizes etc.). As a result, the system's performance is increased by up to 46%. Unlike other approaches we have implemented our engine as a soft IP core such that it can be used directly within a SOC design without any modification on the CPU architecture.

REFERENCES

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Design studies

Additional Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Performance attributes

General Terms:
Design, Experimentation, Performance