Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description

Full text

Pdf (136 KB)

Source

International Symposium on Systems Synthesis archive
Proceedings of the 14th international symposium on Systems synthesis table of contents

Montréal, P.Q., Canada

Session: H/S Embedded Systems table of contents

Pages: 57 - 62

Year of Publication: 2001

ISBN:1-58113-418-5

Authors

Gunnar Braun	Aachen University of Technology (RWTH), Aachen, Germany
Andreas Hoffmann	Aachen University of Technology (RWTH), Aachen, Germany
Achim Nohl	Aachen University of Technology (RWTH), Aachen, Germany
Heinrich Meyr	Aachen University of Technology (RWTH), Aachen, Germany

Sponsors

IEEE : IEEE Computer Society Technical Committee on Design Automation
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 32, Citation Count: 6

Additional Information:

abstract references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/500001.500014 What is a DOI?

ABSTRACT

Instruction set simulators are indispensable tools for both the design of programmable architectures and software development. However, due to a constantly increasing processor complexity and the frequent demand for cycle-accurate models, such simulators have become defectively slow. The principle of compiled simulation addresses this shortcoming. Compiled simulators make use of a priori knowlegde to accelerate simulation, with the highest efficiency achieved by employing static scheduling techniques.In the past, such statically scheduled simulators have only been implemented for specific DSP architectures. The approach presented here discusses the application of static scheduling techniques to retargetable simulation tools based on the processor description language LISA. Principles and implementation issues are discussed in this paper, and results are presented for two selected processor architectures.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Frank Engel , Johannes Nührenberg , Gerhard P. Fettweis, A generic tool set for application specific processor architectures, Proceedings of the eighth international workshop on Hardware/software codesign, p.126-130, May 2000, San Diego, California, United States [doi>10.1145/334012.334036]
	2	M. Freericks. The nML machine description formalism. Technical Report 1991/15, Technische Universitat Berlin, Fachbereich Informatik, Berlin, 1991.
	3	George Hadjiyiannis , Pietro Russo , Srinivas Devadas, A methodology for accurate performance evaluation in architecture exploration, Proceedings of the 36th ACM/IEEE conference on Design automation, p.927-932, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310100]
	4	Ashok Halambi , Peter Grun , Vijay Ganesh , Asheesh Khare , Nikil Dutt , Alex Nicolau, EXPRESSION: a language for architecture exploration through compiler/simulator retargetability, Proceedings of the conference on Design, automation and test in Europe, p.100-es, January 1999, Munich, Germany [doi>10.1145/307418.307549]
	5	Mark R. Hartoog , James A. Rowson , Prakash D. Reddy , Soumya Desai , Douglas D. Dunlop , Edwin A. Harcourt , Neeti Khullar, Generation of software tools from processor descriptions for hardware/software codesign, Proceedings of the 34th annual conference on Design automation, p.303-306, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266110]
	6	A. Hoffmann, A. Nohl, G. Braun, and H. Meyr. A survey on modeling issues using the machine description language LISA. In Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Salt Lake City, USA, May 2001.
	7	A. Khare and N. Savoiu. V-SAT: A visual specification and analysis tool for system-on-chip exploration. In Proceedings of the 25th Euromicro Conference, Milan, Italy, Sep. 1999.
	8	R. Leupers, J. Elste, and B. Landwehr. Generation of interpretive and compiled instruction set simulators. In Proceedings of the Asia and South Pacif ic Design Automation Conference (ASP-DAC), Jan. 1999.
	9	Stefan Pees , Andreas Hoffmann , Heinrich Meyr, Retargeting of compiled simulators for digital signal processors using a machine description language, Proceedings of the conference on Design, automation and test in Europe, p.669-673, March 27-30, 2000, Paris, France [doi>10.1145/343647.343888]
	10	S. Pees, V. Zivojnovic, A. Ropers, and H. Meyr. Fast simulation of the TI TMS320C54x DSP. In Proc. Int. Conf. on Signal Processing Application and Technology (ICSPAT), pages 995-999, San Diego, Sep. 1997.
	11	V. Rajesh , R. Moona, Processor Modeling for Hardware Software Codesign, Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance', p.132, January 10-13, 1999
	12	J. Rowson. Hardware/Software co-simulation. In Proc. of the ACM/IEEE Design Automation Conference (DAC), 1994.
	13	Eric C. Schnarr , Mark D. Hill , James R. Larus, Facile: a language and compiler for high-performance processor simulators, Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation, p.321-331, June 2001, Snowbird, Utah, United States
	14	Chuck Siska, A processor desription language supporting retargetable multi-pipeline DSP program development tools, Proceedings of the 11th international symposium on System synthesis, p.31-36, December 02-04, 1998, Hsinchu, Taiwan, China
	15	Richard L. Sites , Anton Chernoff , Matthew B. Kirk , Maurice P. Marks , Scott G. Robinson, Binary translation, Communications of the ACM, v.36 n.2, p.69-81, Feb. 1993 [doi>10.1145/151220.151227]

CITED BY 6

	Mehrdad Reshadi , Prabhat Mishra, Memory access optimizations in instruction-set simulators, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
	Achim Nohl , Gunnar Braun , Oliver Schliebusch , Rainer Leupers , Heinrich Meyr , Andreas Hoffmann, A universal technique for fast and flexible instruction-set architecture simulation, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Jun Kyoung Kim , Tag Gon Kim, Trace-driven rapid pipeline architecture evaluation scheme for ASIP design, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Mehrdad Reshadi , Prabhat Mishra , Nikil Dutt, Instruction set compiled simulation: a technique for fast and flexible instruction set simulation, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	In-Cheol Park , Sehyeon Kang , Yongseok Yi, Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.138, November 09-13, 2003
	Mehrdad Reshadi , Prabhat Mishra , Nikil Dutt, Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation, ACM Transactions on Embedded Computing Systems (TECS), v.8 n.3, p.1-27, April 2009