|
ABSTRACT
The differences between and appropriateness of branching versus linear time temporal logic for reasoning about concurrent programs are studied. These issues have been previously considered by Lamport. To facilitate a careful examination of these issues, a language, CTL*, in which a universal or existential path quantifier can prefix an arbitrary linear time assertion, is defined. The expressive power of a number of sublanguages is then compared. CTL* is also related to the logics MPL of Abrahamson and PL of Harel, Kozen, and Parikh. The paper concludes with a comparison of the utility of branching and linear time temporal logics.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
|
 |
2
|
|
| |
3
|
|
 |
4
|
|
| |
5
|
EMERSON, E. A. Alternative semantics for temporal logics. Theor. Comput. Sci. 26 (1983), 121-130.
|
| |
6
|
|
| |
7
|
|
| |
8
|
EMERSON, E. A., AND CLARKE, E.M. Using branching time logic to synthesize synchronization skeletons. Sci. Comput. Prog. 2 (1982), 241-266.
|
 |
9
|
|
| |
10
|
|
 |
11
|
|
| |
12
|
EMERSON, E. A., AND SIS'rLA, A.P. Deciding full branching time logic. Inf. Control 61, 3 (1984), 175-201.
|
| |
13
|
FISCHER, M. J., AND LADNER, R.E. Propositional dynamic logic of regular programs. J. Comput. Syst. Sci. 18 (1979), 194-211.
|
 |
14
|
Dov Gabbay , Amir Pnueli , Saharon Shelah , Jonathan Stavi, On the temporal analysis of fairness, Proceedings of the 7th ACM SIGPLAN-SIGACT symposium on Principles of programming languages, p.163-173, January 28-30, 1980, Las Vegas, Nevada
[doi> 10.1145/567446.567462]
|
| |
15
|
HAILPERN, B., AND OWICKI, S. Modular verification of concurrent programs using temporal logic. Tech. Rep., Stanford Univ. Stanford, Calif., 1981.
|
| |
16
|
HAREL, D., KOZEN, D., AND PARXK,, R. Process logic: Expressiveness, decidability, and completeness. J. Comput. Syst. Sci. 25 (1982), 144-170.
|
| |
17
|
HAREL, D., AND SHERMAN, R. Looping vs. repeating in dynamic logic. Inf. Control 55 (1982), 175-192.
|
| |
18
|
KAMP, H. Tense logic and the theory of linear order. Ph.D. dissertation, UCLA, Los Angeles, 1968.
|
 |
19
|
|
| |
20
|
LEHMANN, D., AND SHELAH, S. Reasoning with time and chance. Inf. Control 53 (1982), 165-198.
|
| |
21
|
|
 |
22
|
|
 |
23
|
|
| |
24
|
PNUELI, A. The temporal logic of programs. In Proceedings of the 19th Annual Symposium on Foundations of Computer Science. IEEE, New York, 1977, pp. 46-57.
|
| |
25
|
PNUELI, A. The temporal semantics of concurrent programs. Theor. Comput. Sci. 13 ( 198 l), 45- 60.
|
 |
26
|
|
| |
27
|
PRIOR, A. Time and Modality. Oxford Univ. Press, London, 1957.
|
| |
28
|
PRIOR, A. Past, Present, and Future. Oxford Univ. Press, London, 1967.
|
| |
29
|
RESCHER, N., AND URQUHART, A. Temporal logic. Springer-Verlag, Berlin, 197 I.
|
 |
30
|
|
 |
31
|
|
| |
32
|
|
 |
33
|
|
| |
34
|
WOLPER, P. Temporal logic can be more expressive. Inf. Control 56, 1/2 (1983), 72-99.
|
CITED BY 89
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
E M Clarke , O Grumberg , M C Browne, Reasoning about networks with many identical finite-state processes, Proceedings of the fifth annual ACM symposium on Principles of distributed computing, p.240-248, August 11-13, 1986, Calgary, Alberta, Canada
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Foto Afrati , Theodore Andronikos , Vassia Pavlaki , Eugenie Foustoucos , Irène Guessarian, From CTL to datalog, Proceedings of the Paris C. Kanellakis memorial workshop on Principles of computing & knowledge: Paris C. Kanellakis memorial workshop on the occasion of his 50th birthday, p.72-85, June 08-08, 2003, San Diego, California, USA
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Cinzia Bernardeschi , Alessandro Fantechi , Stefania Gnesi , Salvatore Larosa , Giorgio Mongardi , Dario Romano, A Formal Verification Environment for Railway Signaling System Design, Formal Methods in System Design, v.12 n.2, p.139-161, March 1, 1998
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
REVIEW
"Ali Mili : Reviewer"
This paper extends earlier work by Lamport [1] on comparing two logics of
concurrent programming: Branching Temporal Logic and Linear Time Temporal
Logic. In order to carry out the comparisons, the paper introduces a
special-purpose temporal not
more...
|