The ultimate RISC

ABSTRACT

Reduced instruction set computer (RISC) architectures have attracted considerable interest during the past decade. The ultimate RISC architecture presented here is an extreme yet simple illustration of such an architecture. It has only one instruction, move memory to memory, yet it is useful.

REFERENCES

• 1: [1] PDP-11 Architecture Handbook. Digital Equipment Corporation, Maynard, Mass. 1983.
• 2: John Hennessy , Norman Jouppi , Forest Baskett , Thomas Gross , John Gill, Hardware/software tradeoffs for increased performance, Proceedings of the first international symposium on Architectural support for programming languages and operating systems, p.2-11, March 01-03, 1982, Palo Alto, California, United States
• 3: [3] Introduction to the IAPX 432 Architecture. Intel Corporation, Santa Clara, Calif. 1981.
• 4: Richard K. Johnsson , John D. Wick, An overview of the mesa processor architecture, Proceedings of the first international symposium on Architectural support for programming languages and operating systems, p.20-29, March 01-03, 1982, Palo Alto, California, United States
• 5: Douglas W. Jones, Systematic protection mechanism design, Proceedings of the first international symposium on Architectural support for programming languages and operating systems, p.77-80, March 01-03, 1982, Palo Alto, California, United States
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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: Instruction set design (e.g., RISC, CISC, VLIW)

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.1 Single Data Stream Architectures
          Subjects: Pipeline processors**
          Nouns: RISC**

General Terms:
Design, Performance