Analysis and implementation of charge recycling for deep sub-micron buses

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Analysis and implementation of charge recycling for deep sub-micron buses

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2001 international symposium on Low power electronics and design table of contents

Huntington Beach, California, United States

Pages: 364 - 369

Year of Publication: 2001

ISBN:1-58113-371-5

Authors

Paul Sotiriadis	Department of EECS, Massachusetts Inst. of Technology
Theodoros Konstantakopoulos	Department of EECS, Massachusetts Inst. of Technology
Anantha Chandrakasan	Department of EECS, Massachusetts Inst. of Technology

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 11, Citation Count: 7

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Hui Zhang , Jan Rabaey, Low-swing interconnect interface circuits, Proceedings of the 1998 international symposium on Low power electronics and design, p.161-166, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280876]
	2	Y.Nakagome,K.Itoh,M.Isoda,K.Takeuchi,M.Aoki, "Sub-1-V swing internal bus architecture for future lowpower ULSI's," IEEE Journal of Solid-State Circuits, pp. 414-419, April 1993.
	3	H. Yamauchi, H. Akamatsu, T. Fujita,"An asymptotically zero power charge-recycling bus architecture for batteryoperated ultrahigh data rate ULSI's", Journal of Solid-State Circuits, IEEE, Vol. 30 Issue: 4, pp. 423 -431, April 1995.
	4	Kei-Yong Khoo , Alan N. Wilson, Jr., Charge recovery on a databus, Proceedings of the 1995 international symposium on Low power design, p.185-189, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224114]
	5	Benjamin Bishop , Mary Jane Irwin, Databus charge recovery: practical considerations, Proceedings of the 1999 international symposium on Low power electronics and design, p.85-87, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.314068]
	6	Mircea R. Stan , Wayne P. Burleson, Low-power encodings for global communication in CMOS VLSI, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.5 n.4, p.444-455, Dec. 1997 [doi>10.1109/92.645071]
	7	P. Sotiriadis, A. Wang, A. Chandrakasan, "Transition Pattern Coding: An approach to reduce Energy in Interconnect", ESSCIRC 2000.
	8	Sumant Ramprasad , Naresh R. Shanbhag , Ibrahim N. Hajj, A coding framework for low-power address and data busses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.2, p.212-221, June 1999 [doi>10.1109/92.766748]
	9	Jan M. Rabaey, Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
	10	H.B. Bakoglou, Circuits, Interconnections, and Packaging in VLSI. Addison-Wesley Pub. Co., 1990
	11	Eric Kusse , Jan Rabaey, Low-energy embedded FPGA structures, Proceedings of the 1998 international symposium on Low power electronics and design, p.155-160, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280873]

CITED BY 7

	Paul P. Sotiriadis , Anantha P. Chandrakasan, A bus energy model for deep submicron technology, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.341-350, June 2002
	Himanshu Kaul , Dennis Sylvester , Mark Anders , Ram Krishnamurthy, Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Roshan Weerasekera , Dinesh Pamunuwa , Li-Rong Zheng , Hannu Tenhunen, Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime, Proceedings of the international workshop on System-level interconnect prediction, March 04-05, 2006, Munich, Germany
	Himanshu Kaul , Dennis Sylvester , Mark A. Anders , Ram K. Krishnamurthy, Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.11, p.1225-1238, November 2005
	Himanshu Kaul , Dennis Sylvester , David Blaauw , Trevor Mudge , Todd Austin, DVS for On-Chip Bus Designs Based on Timing Error Correction, Proceedings of the conference on Design, Automation and Test in Europe, p.80-85, March 07-11, 2005
	Kimish Patel , Wonbok Lee , Massoud Pedram, In-order pulsed charge recycling in off-chip data buses, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
	Roshan Weerasekera , Dinesh Pamunuwa , Li-Rong Zheng , Hannu Tenhunen, Minimal-power, delay-balanced SMART repeaters for global interconnects in the nanometer regime, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.5, p.589-593, May 2008