Clocking strategies and scannable latches for low power appliacations

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Clocking strategies and scannable latches for low power appliacations

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2001 international symposium on Low power electronics and design table of contents

Huntington Beach, California, United States

Pages: 346 - 351

Year of Publication: 2001

ISBN:1-58113-371-5

Authors

V. Zyuban	IBM Research Division, T.J. Watson Research Center, Yorktown Heights, NY
D. Meltzer	Epson Research and Development, NY and IBM Research Division, T.J. Watson Research Center, Yorktown Heights, NY

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 22, Citation Count: 6

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. Faris. Circuit design for full scan ATPG. In Forth Annual IEEE International ASIC Conference, pages 6.1-6.4, 1991.
	2	T. Lang, E. Musoll, and J. Cortadella. Individual flip-flops with gated clocks for low power datapaths. IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, 44(6):507-516, June 1997.
	3	Jiing-Yuan Lin , Tai-Chien Liu , Wen-Zen Shen, A cell-based power estimation in CMOS combinational circuits, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.304-309, November 06-10, 1994, San Jose, California, United States
	4	Dynamic Flip-Flop with Improved Power, Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors, p.323, September 17-20, 2000
	5	N. Nedovic , V. G. Oklobdzija, Hybrid latch Flip-Flop with Improved Power Efficiency, Proceedings of the 13th symposium on Integrated circuits and systems design, p.211, September 18-24, 2000
	6	B. Nikolic et al. Improved sense-amplifier-based flip-flop: Design and measurements. IEEE Journal of Solid-State Circuits, 35(6):876-883, June 2000.
	7	Janardhan H. Satyanarayana , Keshab K. Parhi, HEAT: hierarchical energy analysis tool, Proceedings of the 33rd annual conference on Design automation, p.9-14, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240520]
	8	V. Stojanovic and V. Oklobdzija. Comparative analysis of masterslave latches and flip-flops for high-performance and low-power systems. IEEE Journal of Solid-State Circuits, 34(4):536-548, April 1999.
	9	Vladimir Stojanovic , Vojin G. Oklobdzija , Raminder Bajwa, A unified approach in the analysis of latches and flip-flops for low-power systems, Proceedings of the 1998 international symposium on Low power electronics and design, p.227-232, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280911]
	10	C. Svensson and J. Yuan. Latches and flip-flops for low power systems. In A. Chandrakasan and R. Brodersen, editors, Low Power CMOS Design, pages 233-238. IEEE Press, 1998.
	11	J. Yuan and C. Svensson. New single-clock CMOS latches and flipflops with improved speed and power savings. IEEE Journal of Solid-State Circuits, 32(1):62-69, January 1997.
	12	V. Zyuban , P. Kogge, Application of STD to latch-power estimation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.1, p.111-115, March 1999 [doi>10.1109/92.748206]

CITED BY 6

	Victor Zyuban , Stephen V. Kosonocky, Low power integrated scan-retention mechanism, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Victor Zyuban, Optimization of scannable latches for low energy, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.778-788, October 2003
	V. Zyuban , P. N. Strenski, Balancing hardware intensity in microprocessor pipelines, IBM Journal of Research and Development, v.47 n.5-6, p.585-598, September 2003
	Victor Zyuban , Philip Strenski, Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	S. V. Kosonocky , A. J. Bhavnagarwala , K. Chin , G. D. Gristede , A.-M. Haen , W. Hwang , M. B. Ketchen , S. Kim , D. R. Knebel , K. W. Warren , V. Zyuban, Low-power circuits and technology for wireless digital systems, IBM Journal of Research and Development, v.47 n.2-3, p.283-298, March 2003
	Viji Srinivasan , David Brooks , Michael Gschwind , Pradip Bose , Victor Zyuban , Philip N. Strenski , Philip G. Emma, Optimizing pipelines for power and performance, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey